component
NV24C32DWVLT3G
Public Made by Adomby adom
onsemi EEPROM, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNV24C32DWVLT3G
onsemi · EEPROM · SOIC-8
NV24C32DWVLT3G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input that must match slave address bit A0, hard-wired HIGH or LOW, and pulled LOW internally when left floating. |
| 2 | A1 | input | Device address input that must match slave address bit A1, hard-wired HIGH or LOW, and pulled LOW internally when left floating. |
| 3 | A2 | input | Device address input that must match slave address bit A2, hard-wired HIGH or LOW, and pulled LOW internally when left floating. |
| 4 | VSS | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data I/O pin that accepts input data and delivers output data, open drain in transmit mode, with data acquired on the positive SCL edge and delivered on the negative edge. |
| 6 | SCL | input | Serial clock input that accepts the clock signal generated by the master. |
| 7 | WP | input | Write protect input that inhibits all write operations when pulled HIGH and is pulled LOW internally when left floating. |
| 8 | VCC | power_in | Power supply, 1.7 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Read Current | ICCR | 1 | mA | Read, fSCL = 1 MHz | 3 | ||
| Write Current | ICCW | 1 | mA | Write, fSCL = 1 MHz | 3 | ||
| Standby Current | ISB | 2 | µA | All I/O Pins at GND or VCC | 3 | ||
| I/O Pin Leakage | IL | 2 | µA | Pin at GND or VCC | 3 | ||
| Input Low Voltage (minimum) | VIL | -0.5 | V | SCL, SDA; max is VCC x 0.3 | 3 | ||
| Output Low Voltage 1 | VOL1 | 0.4 | V | VCC ≥ 2.5 V, IOL = 3.0 mA | 3 | ||
| Output Low Voltage 2 | VOL2 | 0.2 | V | VCC < 2.5 V, IOL = 1.0 mA | 3 | ||
| SDA I/O Pin Capacitance | CIN | 8 | pF | VIN = 0 V | 3 | ||
| Input Capacitance (other pins) | CIN | 6 | pF | VIN = 0 V | 3 | ||
| Clock Frequency, Standard | FSCL | 100 | kHz | Standard | 4 | ||
| Clock Frequency, Fast | FSCL | 400 | kHz | Fast | 4 | ||
| Clock Frequency, Fast-Plus | FSCL | 1000 | kHz | Fast-Plus | 4 | ||
| Write Cycle Time | tWR | 4 | ms | 4 | |||
| Supply Voltage Range | VCC | 1.7 | 5.5 | V | TA = -40°C to +125°C | 3 | |
| Operating Temperature | TA | -40 | 125 | °C | Automotive AEC-Q100 Grade 1 | 1 | |
| Storage Temperature | Tstg | -65 | 150 | °C | 2 | ||
| Voltage on Any Pin with Respect to Ground | -0.5 | 6.5 | V | Note 1 | 2 | ||
| Endurance | NEND | 1e+06 | Write Cycles | TA = 25°C | 2 | ||
| Data Retention | TDR | 100 | Years | TA = 25°C | 2 |
CAD (KiCad official)
- Symbol:
NV24C32DWVLT3G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
nv24c32dwvlt3g-etched.step/nv24c32dwvlt3g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nv24c32dwvlt3g.step/nv24c32dwvlt3g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
13fdb80ab75dac2a, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).