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NUP4106DR2G
Public Made by Adomby adom
TECH PUBLIC Electrostatic And Surge Protection (TVS/ESD), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NUP4106DR2G
TECH PUBLIC · Electrostatic And Surge Protection (TVS/ESD) · SOP-8
NUP4106DR2G from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O 1 | passive | Protected line 1 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 2 | REF 1 | passive | Reference 1 terminal of the diode steering array, internally connected to pin 3, on the common side of the I/O steering diodes. |
| 3 | REF 1 | passive | Reference 1 terminal of the diode steering array, internally connected to pin 2, on the common side of the I/O steering diodes. |
| 4 | I/O 2 | passive | Protected line 2 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 5 | REF 2 | power_in | Reference 2 terminal shown with a ground symbol in the schematic, internally connected to pin 8, serving as the ground return for clamping. |
| 6 | I/O 3 | passive | Protected line 3 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 7 | I/O 4 | passive | Protected line 4 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 8 | REF 2 | power_in | Reference 2 terminal shown with a ground symbol in the schematic, internally connected to pin 5, serving as the ground return for clamping. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | TVS/Fuse/Board Level Protection |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
NUP4106DR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
nup4106dr2g-etched.step/nup4106dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nup4106dr2g.step/nup4106dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TECH PUBLIC datasheet (4 pp, sha256
42530e55c83795fa, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NUP4106DR2G
**TECH PUBLIC** · Electrostatic And Surge Protection (TVS/ESD) · SOP-8
NUP4106DR2G from TECH PUBLIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O 1 | passive | Protected line 1 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 2 | REF 1 | passive | Reference 1 terminal of the diode steering array, internally connected to pin 3, on the common side of the I/O steering diodes. |
| 3 | REF 1 | passive | Reference 1 terminal of the diode steering array, internally connected to pin 2, on the common side of the I/O steering diodes. |
| 4 | I/O 2 | passive | Protected line 2 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 5 | REF 2 | power_in | Reference 2 terminal shown with a ground symbol in the schematic, internally connected to pin 8, serving as the ground return for clamping. |
| 6 | I/O 3 | passive | Protected line 3 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 7 | I/O 4 | passive | Protected line 4 input/output, with reverse working voltage of 3.3 V max and junction capacitance of 7 pF max to ground. |
| 8 | REF 2 | power_in | Reference 2 terminal shown with a ground symbol in the schematic, internally connected to pin 5, serving as the ground return for clamping. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TECH PUBLIC |
| Package | SOP-8 |
| Category | TVS/Fuse/Board Level Protection |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `NUP4106DR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `nup4106dr2g-etched.step` / `nup4106dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nup4106dr2g.step` / `nup4106dr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TECH PUBLIC datasheet](docs/nup4106dr2g-datasheet.pdf) (4 pp, sha256 `42530e55c83795fa`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/nup4106dr2g-datasheet.pdf)