NUC131SD2AE

Nuvoton Tech · Microcontrollers (MCU/MPU/SOC) · LQFP-64(7x7)

NUC131SD2AE from Nuvoton Tech, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PB.14	bidirectional	General purpose digital I/O pin, also external interrupt 0 input (INT0).
2	PB.13	bidirectional	General purpose digital I/O pin.
3	PB.12	bidirectional	General purpose digital I/O pin; alternate functions are CLKO frequency divider clock output and BPWM1_CH3 output/capture input.
4	PF.5	bidirectional	General purpose digital I/O pin; alternate functions are I2C0_SCL clock and PWM1_CH5 output/capture input.
5	PF.4	bidirectional	General purpose digital I/O pin; alternate functions are I2C0_SDA data and PWM1_CH4 output/capture input.
6	PA.11	bidirectional	General purpose digital I/O pin; alternate functions are I2C1_SCL clock and PWM1_CH3 output/capture input.
7	PA.10	bidirectional	General purpose digital I/O pin; alternate functions are I2C1_SDA data and PWM1_CH2 output/capture input.
8	PA.9	bidirectional	General purpose digital I/O pin; alternate functions are I2C0_SCL clock and UART1_nCTS clear-to-send input.
9	PA.8	bidirectional	General purpose digital I/O pin; alternate functions are I2C0_SDA data and UART1_nRTS request-to-send output.
10	PB.4	bidirectional	General purpose digital I/O pin; alternate function is UART1_RXD data receiver input.
11	PB.5	bidirectional	General purpose digital I/O pin; alternate function is UART1_TXD data transmitter output.
12	PB.6	bidirectional	General purpose digital I/O pin; alternate function is UART1_nRTS request-to-send output.
13	PB.7	bidirectional	General purpose digital I/O pin; alternate function is UART1_nCTS clear-to-send input.
14	LDO_CAP	power_out	LDO output pin for the internal 1.8 V LDO shown in the block diagram.
15	VDD	power_in	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
16	VSS	power_in	Ground pin for digital circuit.
17	PB.0	bidirectional	General purpose digital I/O pin; alternate function is UART0_RXD data receiver input.
18	PB.1	bidirectional	General purpose digital I/O pin; alternate function is UART0_TXD data transmitter output.
19	PB.2	bidirectional	General purpose digital I/O pin; alternate functions are UART0_nRTS output, TM2_EXT capture input, TM2 toggle output and PWM1_BRAKE1 brake input.
20	PB.3	bidirectional	General purpose digital I/O pin; alternate functions are UART0_nCTS input, TM3_EXT capture input, TM3 toggle output and PWM1_BRAKE0 brake input.
21	PD.6	bidirectional	General purpose digital I/O pin; alternate functions are CAN0_RXD receiver input and BPWM1_CH1 output/capture input.
22	PD.7	bidirectional	General purpose digital I/O pin; alternate functions are CAN0_TXD transmitter output and BPWM1_CH0 output/capture input.
23	PD.14	bidirectional	General purpose digital I/O pin; alternate functions are UART2_RXD receiver input and BPWM0_CH5 output/capture input.
24	PD.15	bidirectional	General purpose digital I/O pin; alternate functions are UART2_TXD transmitter output and BPWM0_CH4 input/capture input.
25	PC.3	bidirectional	General purpose digital I/O pin; alternate functions are SPI0_MOSI0 master-out/slave-in and BPWM0_CH3 output/capture.
26	PC.2	bidirectional	General purpose digital I/O pin; alternate functions are SPI0_MISO0 master-in/slave-out and BPWM0_CH2 input/capture.
27	PC.1	bidirectional	General purpose digital I/O pin; alternate functions are SPI0_CLK serial clock and BPWM0_CH1 input/capture.
28	PC.0	bidirectional	General purpose digital I/O pin; alternate functions are SPI0_SS0 slave select and BPWM0_CH0 input/capture.
29	PE.5	bidirectional	General purpose digital I/O pin; alternate functions are PWM0_CH5 output/capture, TM1_EXT capture input and TM1 toggle output.
30	PB.11	bidirectional	General purpose digital I/O pin; alternate functions are TM3 event counter input/toggle output and PWM0_CH4 output/capture.
31	PB.10	bidirectional	General purpose digital I/O pin; alternate function is TM2 event counter input/toggle output.
32	PB.9	bidirectional	General purpose digital I/O pin; alternate function is TM1 event counter input/toggle output.
33	PC.11	bidirectional	General purpose digital I/O pin; alternate function is PWM1_BRAKE1 brake input.
34	PC.10	bidirectional	General purpose digital I/O pin; alternate function is PWM1_BRAKE0 brake input.
35	PC.9	bidirectional	General purpose digital I/O pin; alternate function is PWM0_BRAKE1 brake input.
36	PC.8	bidirectional	General purpose digital I/O pin; alternate function is PWM0_BRAKE0 brake input.
37	PA.15	bidirectional	General purpose digital I/O pin; alternate function is PWM0_CH3 output/capture input.
38	PA.14	bidirectional	General purpose digital I/O pin; alternate function is PWM0_CH2 output/capture input.
39	PA.13	bidirectional	General purpose digital I/O pin; alternate functions are PWM0_CH1 output/capture input and UART5_TXD transmitter output.
40	PA.12	bidirectional	General purpose digital I/O pin; alternate functions are PWM0_CH0 output/capture input and UART5_RXD receiver input.
41	PF.7	bidirectional	General purpose digital I/O pin; alternate function is ICE_DAT serial wire debugger data.
42	PF.6	bidirectional	General purpose digital I/O pin; alternate function is ICE_CLK serial wire debugger clock input.
43	AVSS	power_in	Ground pin for analog circuit.
44	PA.0	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH0 analog input, PWM0_CH4 output/capture, I2C1_SCL clock and UART5_TXD transmitter output.
45	PA.1	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH1 analog input, PWM0_CH5 output/capture, I2C1_SDA data and UART5_RXD receiver input.
46	PA.2	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH2 analog input, PWM1_CH0 output/capture and UART3_TXD transmitter output.
47	PA.3	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH3 analog input, PWM1_CH1 output/capture and UART3_RXD receiver input.
48	PA.4	bidirectional	General purpose digital I/O pin; alternate function is ADC_CH4 analog input.
49	PA.5	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH5 analog input and UART3_RXD receiver input.
50	PA.6	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH6 analog input and UART3_TXD transmitter output.
51	PA.7	bidirectional	General purpose digital I/O pin; alternate functions are ADC_CH7 analog input and VREF voltage reference input for the ADC.
52	AVDD	power_in	Power supply for internal analog circuit.
53	PC.7	bidirectional	General purpose digital I/O pin; alternate functions are UART4_RXD receiver input, I2C0_SCL clock and PWM0_BRAKE1 brake input.
54	PC.6	bidirectional	General purpose digital I/O pin; alternate functions are UART4_TXD transmitter output, I2C0_SDA data and PWM0_BRAKE0 brake input.
55	PC.15	bidirectional	General purpose digital I/O pin.
56	PC.14	bidirectional	General purpose digital I/O pin.
57	PB.15	bidirectional	General purpose digital I/O pin; alternate functions are INT1 external interrupt 1 input, TM0_EXT capture input, TM0 toggle output and BPWM1_CH5 output/capture.
58	PF.0	bidirectional	General purpose digital I/O pin; alternate function is XT1_OUT output for the external 4~24 MHz (high speed) crystal.
59	PF.1	bidirectional	General purpose digital I/O pin; alternate function is XT1_IN input for the external 4~24 MHz (high speed) crystal.
60	nRESET	input	External reset input, active LOW with an internal pull-up; driving it low resets the chip to its initial state.
61	VSS	power_in	Ground pin for digital circuit.
62	VDD	power_in	Power supply for I/O ports and LDO source for internal PLL and digital circuit.
63	PF.8	bidirectional	General purpose digital I/O pin; alternate functions are CLKO frequency divider clock output and BPWM1_CH4 output/capture input.
64	PB.8	bidirectional	General purpose digital I/O pin; alternate functions are STADC ADC external trigger input, TM0 event counter/toggle, CLKO output and BPWM1_CH2 output/capture.

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	LQFP-64(7x7)
Category	Embedded Processors & Controllers
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DC Power Supply	VDD-VSS	-0.3		7	V		55
Input Voltage	VIN	-0.3		0.3	V	Printed as VSS-0.3 (min) and VDD+0.3 (max); numeric offsets relative to VSS and VDD	55
Oscillator Frequency	1/tCLCL	4		24	MHz		55
Operating Temperature	TA	-40		105	C		55
Storage Temperature	TST	-55		150	C		55
Maximum Current into VDD				120	mA		55
Maximum Current out of VSS				120	mA		55
Maximum Current sunk by a I/O pin				35	mA		55
Maximum Current sourced by a I/O pin				35	mA		55
Maximum Current sunk by total I/O pins				100	mA		55
Maximum Current sourced by total I/O pins				100	mA		55
Operation Voltage	VDD	2.5		5.5	V	VDD = 2.5V ~ 5.5V up to 50 MHz	56
Operation Voltage (external crystal)	VHXT	2.5		5.5	V		60
Operation Voltage (internal 22.1184 MHz HIRC)	VHRC	2.5		5.5	V		61
Operation Voltage (internal 10 kHz LIRC)	VLRC	2.5		5.5	V		62
Temperature (external crystal)	TA	-40		105	℃		60
Power Ground	VSS	-0.3	0	0.3	V		56
LDO Output Voltage	VLDO	1.62	1.8	1.98	V	VDD ≥ 2.5V	56
Band-gap Voltage	VBG	1.19	1.2	1.22	V	VDD = 2.5 V ~ 5.5 V, TA = -40C~105C	56
Clock Frequency (external crystal)	fHXT	4		24	MHz	External crystal	60
Clock High Time	tCHCX	10			nS		60
Clock Low Time	tCLCX	10			nS		60
Clock Rise Time	tCLCH	2		15	nS		60
Clock Fall Time	tCHCL	2		15	nS		60
Calibrated Internal Oscillator Frequency (22.1184 MHz HIRC)		-1		1	%	+25℃; VDD = 5 V	61
Calibrated Internal Oscillator Frequency (22.1184 MHz HIRC)		-2		2	%	-40℃~~+105℃; VDD = 2.5 V~~5.5 V	61
Calibrated Internal Oscillator Frequency (10 kHz LIRC)		-10		10	%	+25℃; VDD = 5 V	62
Calibrated Internal Oscillator Frequency (10 kHz LIRC)		-50		50	%	-40℃~~+105℃; VDD = 2.5 V~~5.5 V	62
Resolution				12	Bit		63
ADC clock frequency	FADC			21	MHz	AVDD = 4.5V~5.5V	63
Sample rate	FS			1000	kSPS	FADC/TCONV	63
Acquisition Time (Sample Stage)	TACQ	2		9	1/FADC		63
Total Conversion Time	TCONV	16		23	1/FADC		63
Supplt Current	VDDA	3		5.5	V		63
Input voltage (ADC)	VIN	0			V	Maximum printed as AVDD (not numeric)	63
Operating Temperature (LDO)	TA	-40	25	105	℃		64
Supply Voltage (Flash)	VFLA	1.62	1.8	1.98	V	Source from chip LDO output voltage	67
Endurance	NENDUR	20000			cycles		67
Data Retention	TRET	100			year	At 85℃	67
Page Erase Time	TERASE	20			ms		67
Mass Erase Time	TMER	40			ms		67
Program Time	TPROG	40			μs		67
HD;STA START condition hold time	tHD;STA	4			uS	Standard mode	68
HD;STA START condition hold time	tHD;STA	0.6			uS	Fast mode	68
STOP condition setup time	tSU;STO	4			uS	Standard mode	68
STOP condition setup time	tSU;STO	0.6			uS	Fast mode	68
Bus free time	tBUF	4.7			uS	Standard mode	68
Bus free time	tBUF	1.2			uS	Fast mode	68
Data setup time	tSU;DAT	250			nS	Standard mode	68
Data setup time	tSU;DAT	100			nS	Fast mode	68
Data hold time	tHD;DAT	0		3.45	uS	Standard mode	68
Data hold time	tHD;DAT	0		0.8	uS	Fast mode	68
SCL/SDA rise time	tr			1000	nS	Standard mode	68
SCL/SDA rise time	tr			300	nS	Fast mode	68
SCL/SDA fall time	tf			300	nS	Standard mode	68
Capacitive load for each bus line	Cb			400	pF	Standard mode	68

CAD (KiCad official)

Symbol: NUC131SD2AE
Footprint: Package_QFP:LQFP-64_7x7mm_P0.4mm
3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
3D model files: nuc131sd2ae-etched.step / nuc131sd2ae-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nuc131sd2ae.step / nuc131sd2ae.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (75 pp, sha256 c2666ff0fac3cf48, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# NUC131SD2AE

**Nuvoton Tech** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(7x7)

NUC131SD2AE from Nuvoton Tech, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PB.14 | bidirectional | General purpose digital I/O pin, also external interrupt 0 input (INT0). |
| 2 | PB.13 | bidirectional | General purpose digital I/O pin. |
| 3 | PB.12 | bidirectional | General purpose digital I/O pin; alternate functions are CLKO frequency divider clock output and BPWM1_CH3 output/capture input. |
| 4 | PF.5 | bidirectional | General purpose digital I/O pin; alternate functions are I2C0_SCL clock and PWM1_CH5 output/capture input. |
| 5 | PF.4 | bidirectional | General purpose digital I/O pin; alternate functions are I2C0_SDA data and PWM1_CH4 output/capture input. |
| 6 | PA.11 | bidirectional | General purpose digital I/O pin; alternate functions are I2C1_SCL clock and PWM1_CH3 output/capture input. |
| 7 | PA.10 | bidirectional | General purpose digital I/O pin; alternate functions are I2C1_SDA data and PWM1_CH2 output/capture input. |
| 8 | PA.9 | bidirectional | General purpose digital I/O pin; alternate functions are I2C0_SCL clock and UART1_nCTS clear-to-send input. |
| 9 | PA.8 | bidirectional | General purpose digital I/O pin; alternate functions are I2C0_SDA data and UART1_nRTS request-to-send output. |
| 10 | PB.4 | bidirectional | General purpose digital I/O pin; alternate function is UART1_RXD data receiver input. |
| 11 | PB.5 | bidirectional | General purpose digital I/O pin; alternate function is UART1_TXD data transmitter output. |
| 12 | PB.6 | bidirectional | General purpose digital I/O pin; alternate function is UART1_nRTS request-to-send output. |
| 13 | PB.7 | bidirectional | General purpose digital I/O pin; alternate function is UART1_nCTS clear-to-send input. |
| 14 | LDO_CAP | power_out | LDO output pin for the internal 1.8 V LDO shown in the block diagram. |
| 15 | VDD | power_in | Power supply for I/O ports and LDO source for internal PLL and digital circuit. |
| 16 | VSS | power_in | Ground pin for digital circuit. |
| 17 | PB.0 | bidirectional | General purpose digital I/O pin; alternate function is UART0_RXD data receiver input. |
| 18 | PB.1 | bidirectional | General purpose digital I/O pin; alternate function is UART0_TXD data transmitter output. |
| 19 | PB.2 | bidirectional | General purpose digital I/O pin; alternate functions are UART0_nRTS output, TM2_EXT capture input, TM2 toggle output and PWM1_BRAKE1 brake input. |
| 20 | PB.3 | bidirectional | General purpose digital I/O pin; alternate functions are UART0_nCTS input, TM3_EXT capture input, TM3 toggle output and PWM1_BRAKE0 brake input. |
| 21 | PD.6 | bidirectional | General purpose digital I/O pin; alternate functions are CAN0_RXD receiver input and BPWM1_CH1 output/capture input. |
| 22 | PD.7 | bidirectional | General purpose digital I/O pin; alternate functions are CAN0_TXD transmitter output and BPWM1_CH0 output/capture input. |
| 23 | PD.14 | bidirectional | General purpose digital I/O pin; alternate functions are UART2_RXD receiver input and BPWM0_CH5 output/capture input. |
| 24 | PD.15 | bidirectional | General purpose digital I/O pin; alternate functions are UART2_TXD transmitter output and BPWM0_CH4 input/capture input. |
| 25 | PC.3 | bidirectional | General purpose digital I/O pin; alternate functions are SPI0_MOSI0 master-out/slave-in and BPWM0_CH3 output/capture. |
| 26 | PC.2 | bidirectional | General purpose digital I/O pin; alternate functions are SPI0_MISO0 master-in/slave-out and BPWM0_CH2 input/capture. |
| 27 | PC.1 | bidirectional | General purpose digital I/O pin; alternate functions are SPI0_CLK serial clock and BPWM0_CH1 input/capture. |
| 28 | PC.0 | bidirectional | General purpose digital I/O pin; alternate functions are SPI0_SS0 slave select and BPWM0_CH0 input/capture. |
| 29 | PE.5 | bidirectional | General purpose digital I/O pin; alternate functions are PWM0_CH5 output/capture, TM1_EXT capture input and TM1 toggle output. |
| 30 | PB.11 | bidirectional | General purpose digital I/O pin; alternate functions are TM3 event counter input/toggle output and PWM0_CH4 output/capture. |
| 31 | PB.10 | bidirectional | General purpose digital I/O pin; alternate function is TM2 event counter input/toggle output. |
| 32 | PB.9 | bidirectional | General purpose digital I/O pin; alternate function is TM1 event counter input/toggle output. |
| 33 | PC.11 | bidirectional | General purpose digital I/O pin; alternate function is PWM1_BRAKE1 brake input. |
| 34 | PC.10 | bidirectional | General purpose digital I/O pin; alternate function is PWM1_BRAKE0 brake input. |
| 35 | PC.9 | bidirectional | General purpose digital I/O pin; alternate function is PWM0_BRAKE1 brake input. |
| 36 | PC.8 | bidirectional | General purpose digital I/O pin; alternate function is PWM0_BRAKE0 brake input. |
| 37 | PA.15 | bidirectional | General purpose digital I/O pin; alternate function is PWM0_CH3 output/capture input. |
| 38 | PA.14 | bidirectional | General purpose digital I/O pin; alternate function is PWM0_CH2 output/capture input. |
| 39 | PA.13 | bidirectional | General purpose digital I/O pin; alternate functions are PWM0_CH1 output/capture input and UART5_TXD transmitter output. |
| 40 | PA.12 | bidirectional | General purpose digital I/O pin; alternate functions are PWM0_CH0 output/capture input and UART5_RXD receiver input. |
| 41 | PF.7 | bidirectional | General purpose digital I/O pin; alternate function is ICE_DAT serial wire debugger data. |
| 42 | PF.6 | bidirectional | General purpose digital I/O pin; alternate function is ICE_CLK serial wire debugger clock input. |
| 43 | AVSS | power_in | Ground pin for analog circuit. |
| 44 | PA.0 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH0 analog input, PWM0_CH4 output/capture, I2C1_SCL clock and UART5_TXD transmitter output. |
| 45 | PA.1 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH1 analog input, PWM0_CH5 output/capture, I2C1_SDA data and UART5_RXD receiver input. |
| 46 | PA.2 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH2 analog input, PWM1_CH0 output/capture and UART3_TXD transmitter output. |
| 47 | PA.3 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH3 analog input, PWM1_CH1 output/capture and UART3_RXD receiver input. |
| 48 | PA.4 | bidirectional | General purpose digital I/O pin; alternate function is ADC_CH4 analog input. |
| 49 | PA.5 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH5 analog input and UART3_RXD receiver input. |
| 50 | PA.6 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH6 analog input and UART3_TXD transmitter output. |
| 51 | PA.7 | bidirectional | General purpose digital I/O pin; alternate functions are ADC_CH7 analog input and VREF voltage reference input for the ADC. |
| 52 | AVDD | power_in | Power supply for internal analog circuit. |
| 53 | PC.7 | bidirectional | General purpose digital I/O pin; alternate functions are UART4_RXD receiver input, I2C0_SCL clock and PWM0_BRAKE1 brake input. |
| 54 | PC.6 | bidirectional | General purpose digital I/O pin; alternate functions are UART4_TXD transmitter output, I2C0_SDA data and PWM0_BRAKE0 brake input. |
| 55 | PC.15 | bidirectional | General purpose digital I/O pin. |
| 56 | PC.14 | bidirectional | General purpose digital I/O pin. |
| 57 | PB.15 | bidirectional | General purpose digital I/O pin; alternate functions are INT1 external interrupt 1 input, TM0_EXT capture input, TM0 toggle output and BPWM1_CH5 output/capture. |
| 58 | PF.0 | bidirectional | General purpose digital I/O pin; alternate function is XT1_OUT output for the external 4~24 MHz (high speed) crystal. |
| 59 | PF.1 | bidirectional | General purpose digital I/O pin; alternate function is XT1_IN input for the external 4~24 MHz (high speed) crystal. |
| 60 | nRESET | input | External reset input, active LOW with an internal pull-up; driving it low resets the chip to its initial state. |
| 61 | VSS | power_in | Ground pin for digital circuit. |
| 62 | VDD | power_in | Power supply for I/O ports and LDO source for internal PLL and digital circuit. |
| 63 | PF.8 | bidirectional | General purpose digital I/O pin; alternate functions are CLKO frequency divider clock output and BPWM1_CH4 output/capture input. |
| 64 | PB.8 | bidirectional | General purpose digital I/O pin; alternate functions are STADC ADC external trigger input, TM0 event counter/toggle, CLKO output and BPWM1_CH2 output/capture. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nuvoton Tech |
| Package | LQFP-64(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Power Supply | VDD-VSS | -0.3 |  | 7 | V |  | 55 |
| Input Voltage | VIN | -0.3 |  | 0.3 | V | Printed as VSS-0.3 (min) and VDD+0.3 (max); numeric offsets relative to VSS and VDD | 55 |
| Oscillator Frequency | 1/tCLCL | 4 |  | 24 | MHz |  | 55 |
| Operating Temperature | TA | -40 |  | 105 | C |  | 55 |
| Storage Temperature | TST | -55 |  | 150 | C |  | 55 |
| Maximum Current into VDD |  |  |  | 120 | mA |  | 55 |
| Maximum Current out of VSS |  |  |  | 120 | mA |  | 55 |
| Maximum Current sunk by a I/O pin |  |  |  | 35 | mA |  | 55 |
| Maximum Current sourced by a I/O pin |  |  |  | 35 | mA |  | 55 |
| Maximum Current sunk by total I/O pins |  |  |  | 100 | mA |  | 55 |
| Maximum Current sourced by total I/O pins |  |  |  | 100 | mA |  | 55 |
| Operation Voltage | VDD | 2.5 |  | 5.5 | V | VDD = 2.5V ~ 5.5V up to 50 MHz | 56 |
| Operation Voltage (external crystal) | VHXT | 2.5 |  | 5.5 | V |  | 60 |
| Operation Voltage (internal 22.1184 MHz HIRC) | VHRC | 2.5 |  | 5.5 | V |  | 61 |
| Operation Voltage (internal 10 kHz LIRC) | VLRC | 2.5 |  | 5.5 | V |  | 62 |
| Temperature (external crystal) | TA | -40 |  | 105 | ℃ |  | 60 |
| Power Ground | VSS | -0.3 | 0 | 0.3 | V |  | 56 |
| LDO Output Voltage | VLDO | 1.62 | 1.8 | 1.98 | V | VDD ≥ 2.5V | 56 |
| Band-gap Voltage | VBG | 1.19 | 1.2 | 1.22 | V | VDD = 2.5 V ~ 5.5 V, TA = -40C~105C | 56 |
| Clock Frequency (external crystal) | fHXT | 4 |  | 24 | MHz | External crystal | 60 |
| Clock High Time | tCHCX | 10 |  |  | nS |  | 60 |
| Clock Low Time | tCLCX | 10 |  |  | nS |  | 60 |
| Clock Rise Time | tCLCH | 2 |  | 15 | nS |  | 60 |
| Clock Fall Time | tCHCL | 2 |  | 15 | nS |  | 60 |
| Calibrated Internal Oscillator Frequency (22.1184 MHz HIRC) |  | -1 |  | 1 | % | +25℃; VDD = 5 V | 61 |
| Calibrated Internal Oscillator Frequency (22.1184 MHz HIRC) |  | -2 |  | 2 | % | -40℃~+105℃; VDD = 2.5 V~5.5 V | 61 |
| Calibrated Internal Oscillator Frequency (10 kHz LIRC) |  | -10 |  | 10 | % | +25℃; VDD = 5 V | 62 |
| Calibrated Internal Oscillator Frequency (10 kHz LIRC) |  | -50 |  | 50 | % | -40℃~+105℃; VDD = 2.5 V~5.5 V | 62 |
| Resolution |  |  |  | 12 | Bit |  | 63 |
| ADC clock frequency | FADC |  |  | 21 | MHz | AVDD = 4.5V~5.5V | 63 |
| Sample rate | FS |  |  | 1000 | kSPS | FADC/TCONV | 63 |
| Acquisition Time (Sample Stage) | TACQ | 2 |  | 9 | 1/FADC |  | 63 |
| Total Conversion Time | TCONV | 16 |  | 23 | 1/FADC |  | 63 |
| Supplt Current | VDDA | 3 |  | 5.5 | V |  | 63 |
| Input voltage (ADC) | VIN | 0 |  |  | V | Maximum printed as AVDD (not numeric) | 63 |
| Operating Temperature (LDO) | TA | -40 | 25 | 105 | ℃ |  | 64 |
| Supply Voltage (Flash) | VFLA | 1.62 | 1.8 | 1.98 | V | Source from chip LDO output voltage | 67 |
| Endurance | NENDUR | 20000 |  |  | cycles |  | 67 |
| Data Retention | TRET | 100 |  |  | year | At 85℃ | 67 |
| Page Erase Time | TERASE | 20 |  |  | ms |  | 67 |
| Mass Erase Time | TMER | 40 |  |  | ms |  | 67 |
| Program Time | TPROG | 40 |  |  | μs |  | 67 |
| HD;STA START condition hold time | tHD;STA | 4 |  |  | uS | Standard mode | 68 |
| HD;STA START condition hold time | tHD;STA | 0.6 |  |  | uS | Fast mode | 68 |
| STOP condition setup time | tSU;STO | 4 |  |  | uS | Standard mode | 68 |
| STOP condition setup time | tSU;STO | 0.6 |  |  | uS | Fast mode | 68 |
| Bus free time | tBUF | 4.7 |  |  | uS | Standard mode | 68 |
| Bus free time | tBUF | 1.2 |  |  | uS | Fast mode | 68 |
| Data setup time | tSU;DAT | 250 |  |  | nS | Standard mode | 68 |
| Data setup time | tSU;DAT | 100 |  |  | nS | Fast mode | 68 |
| Data hold time | tHD;DAT | 0 |  | 3.45 | uS | Standard mode | 68 |
| Data hold time | tHD;DAT | 0 |  | 0.8 | uS | Fast mode | 68 |
| SCL/SDA rise time | tr |  |  | 1000 | nS | Standard mode | 68 |
| SCL/SDA rise time | tr |  |  | 300 | nS | Fast mode | 68 |
| SCL/SDA fall time | tf |  |  | 300 | nS | Standard mode | 68 |
| Capacitive load for each bus line | Cb |  |  | 400 | pF | Standard mode | 68 |

## CAD (KiCad official)

- Symbol: `NUC131SD2AE`
- Footprint: `Package_QFP:LQFP-64_7x7mm_P0.4mm`
- 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
- 3D model files: `nuc131sd2ae-etched.step` / `nuc131sd2ae-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nuc131sd2ae.step` / `nuc131sd2ae.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nuvoton Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590910714548592640) (75 pp, sha256 `c2666ff0fac3cf48`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/nuc131sd2ae-datasheet.pdf)