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Contents

README

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NTA7002NT1G

Leiditech · MOSFETs · SOT-523

NTA7002NT1G from Leiditech, in a SOT-523. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GATE input Gate terminal of the N-channel enhancement MOSFET, with gate-source voltage rated at ±20 V (VGS).
2 SOURCE passive Source terminal of the N-channel MOSFET, referenced by the 30 V drain-source breakdown rating [V(BR)DSS min 30 V at VGS = 0 V, ID = 10 µA].
3 DRAIN passive Drain terminal of the N-channel MOSFET, rated for VDS of 30 V and a drain current of 150 mA per the device summary table, with power dissipation of 0.15 W.

Key specifications

Parameter Value
Manufacturer Leiditech
Package SOT-523
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 30 V Ta = 25°C 1
Gate-Source Voltage VGS -20 20 V Ta = 25°C 1
Power Dissipation PD 0.15 W Ta = 25°C 1
Junction Temperature TJ 150 ℃ 1
Storage Temperature Tstg -55 150 ℃ 1
Thermal Resistance, Junction-to-Ambient RθJA 833 ℃/W 1
Drain-Source Breakdown Voltage V(BR)DSS 30 V VGS = 0V, ID = 10µA 2
Zero Gate Voltage Drain Current IDSS 1 µA VDS =30V, VGS = 0V 2
Gate-Source Leakage Current IGSS -2 2 µA VGS =±20V, VDS = 0V 2
Drain-Source On-Resistance RDS(on) 4 Ω VGS = 10V, ID =200mA 2
Drain-Source On-Resistance RDS(on) 8 Ω VGS =4.5V, ID =150mA 2

CAD (KiCad official)

  • Symbol: NTA7002NT1G
  • Footprint: Package_TO_SOT_SMD:SOT-523
  • 3D model: SOT-523, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.8 mm nominal SOT-523 height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: nta7002nt1g-etched.step / nta7002nt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nta7002nt1g.step / nta7002nt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Leiditech datasheet (3 pp, sha256 5d7c1a13c6043443, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF