component
NSMB05S50M1
Public Made by Adomby adom
WXNSIC Intelligent Power Modules (IPM), SOP-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NSMB05S50M1
WXNSIC · Intelligent Power Modules (IPM) · SOP-23
NSMB05S50M1 from WXNSIC, in a SOP-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COM | power_in | IC common supply ground. |
| 2 | VB(U) | power_in | Bias voltage for U-phase high-side MOSFET driving; VBS rated 20 V max, 10 to 18.5 V recommended. |
| 3 | VCC(U) | power_in | Bias voltage for U-phase IC and low-side MOSFET driving; VCC rated 20 V max, 10 to 18.5 V recommended. |
| 4 | IN(UH) | input | Signal input for U-phase high-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 5 | IN(UL) | input | Signal input for U-phase low-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 6 | N.C | unconnected | No connection. |
| 7 | VB(V) | power_in | Bias voltage for V-phase high-side MOSFET driving; VBS rated 20 V max, 10 to 18.5 V recommended. |
| 8 | VCC(V) | power_in | Bias voltage for V-phase IC and low-side MOSFET driving; VCC rated 20 V max, 10 to 18.5 V recommended. |
| 9 | IN(VH) | input | Signal input for V-phase high-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 10 | IN(VL) | input | Signal input for V-phase low-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 11 | VTS | output | Output for HVIC temperature sensing; 320 to 900 mV (typ 650 mV) at VCC = 15 V, THVIC = 25 °C. |
| 12 | VB(W) | power_in | Bias voltage for W-phase high-side MOSFET driving; VBS rated 20 V max, 10 to 18.5 V recommended. |
| 13 | VCC(W) | power_in | Bias voltage for W-phase IC and low-side MOSFET driving; VCC rated 20 V max, 10 to 18.5 V recommended. |
| 14 | IN(WH) | input | Signal input for W-phase high-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 15 | IN(WL) | input | Signal input for W-phase low-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 16 | N.C | unconnected | No connection. |
| 17 | P | power_in | Positive DC-link input; supply voltage VPN recommended 300 V typ, 400 V max, MOSFET VDSS 500 V. |
| 18 | U,VS(U) | power_out | Output for U-phase and bias voltage ground for high-side MOSFET driving. |
| 19 | NU | passive | Negative DC-link input for U-phase (low-side current sense terminal). |
| 20 | NV | passive | Negative DC-link input for V-phase (low-side current sense terminal). |
| 21 | V,VS(V) | power_out | Output for V-phase and bias voltage ground for high-side MOSFET driving. |
| 22 | NW | passive | Negative DC-link input for W-phase (low-side current sense terminal). |
| 23 | W,VS(W) | power_out | Output for W-phase and bias voltage ground for high-side MOSFET driving. |
| 24 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WXNSIC |
| Package | SOP-23 |
| Category | Transistors/Thyristors |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 500 | V | VGS= 0 V, ID = 250 uA | 6 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | uA | VGS = 0 V, VDS = 500 V | 6 | ||
| Static Drain-Source Turn-On Resistance | RDS(on) | 1.8 | 2.4 | Ω | VCC = VBS = 15V, VIN = 5V, ID =2.5A | 6 | |
| Drain-Source Diode Forward Voltage | VSD | 0.9 | 1.4 | V | VCC = VBS = 15V, ID = -5.0A | 6 | |
| Quiescent VCC Supply Current | IQCC | 100 | 220 | uA | VCC = 15V, VIN= 0V, between VCC and COM | 6 | |
| Quiescent VB Supply Current | IQBS | 50 | 100 | uA | VBS = 15V, VIN = 0V | 6 | |
| HVIC Temperature Sensing Voltage Output | VTS | 320 | 650 | 900 | mV | VCC = 15V, THVIC=25 oC | 6 |
| ON Threshold Voltage Logic HIGH Level | VIH | 2.6 | V | Applied between VIN and COM | 6 | ||
| OFF Threshold Voltage Logic LOW Level | VIL | 0.8 | V | Applied between VIN and COM | 6 | ||
| Supply Voltage | VPN | 300 | 400 | V | Applied between P and N | 5 | |
| Control Supply Voltage | VCC | 10 | 18.5 | V | Applied between VCC and COM | 5 | |
| High-Side Bias Voltage | VBS | 10 | 18.5 | V | Applied between VB and VS | 5 | |
| Input ON Threshold Voltage | VIN(ON) | 3 | V | Applied between VIN and COM (max VCC) | 5 | ||
| Input OFF Threshold Voltage | VIN(OFF) | 0 | 0.6 | V | Applied between VIN and COM | 5 | |
| Drain-Source Voltage of Each MOSFET | VDSS | 500 | V | 5 | |||
| Drain Current, Continuous | ID | 5 | A | TC = 25°C | 5 | ||
| Drain Pulse Current, Peak | IDP | 10 | A | TC = 25°C, Less than 100us | 5 | ||
| Drain Current, Rms | IDRMS | 0.6 | Arms | TC = 80°C, FPWM <20KHz | 5 | ||
| Maximum Power Dissipation | PD | 14 | W | TC = 25°C For each MOSFET | 5 | ||
| Control Supply Voltage | VCC | 20 | V | Applied between VCC and COM | 5 | ||
| High-side Bias Voltage | VBS | 20 | V | Applied between VB and VS | 5 | ||
| Bootstrap Max Repetitive Reverse Voltage | VRRMB | 500 | V | 5 | |||
| Bootstrap Forward Current | IFB | 0.25 | A | TC = 25°C | 5 | ||
| Bootstrap Forward Peak Current | IFPB | 0.5 | A | TC = 25°C,Under 1ms Pulse Width | 5 | ||
| Operating Junction Temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage Temperature | TSTG | -40 | 150 | °C | 5 | ||
| Isolation Voltage | VISO | 1500 | Vrms | 60Hz, Sinusoidal, 1 minute, Connect Pins to Heat-Sink Plate | 5 | ||
| Junction to Case Thermal Resistance | RθJC | 7.1 | °C/W | Each MOSFET under Inverter Operating Condition | 5 | ||
| Turn-on Time | tON | 960 | ns | VPN = 300 V, VCC = VBS = 15 V, ID = 0.5A, IN = 0V↔5V, L = 3 mH | 6 | ||
| Turn-off Time | tOFF | 560 | ns | VPN = 300 V, VCC = VBS = 15 V, ID = 0.5A, IN = 0V↔5V, L = 3 mH | 6 | ||
| Reverse Recovery Time | trr | 230 | ns | VPN = 300 V, VCC = VBS = 15 V, ID = 0.5A, IN = 0V↔5V, L = 3 mH | 6 | ||
| Low-side UVLO Detection Level | VCCD | 7.7 | V | 6 | |||
| Low-side UVLO Reset Level | VCCR | 8.7 | V | 6 | |||
| High-side UVLO Detection Level | VBSD | 7.7 | V | 6 | |||
| High-side UVLO Reset Level | VBSR | 8.7 | V | 6 | |||
| Bootstrap Diode Forward Voltage | VF BSD | 2.8 | V | IF = 0.1 A, TC = 25°C | 6 | ||
| Bootstrap Diode Reverse Recovery Time | trrB | 80 | ns | IF = 0.1 A, TC = 25°C | 6 | ||
| Bootstrap Current Limiting Resistor | R BSD | 18 | ohm | 6 |
CAD (KiCad official)
- Symbol:
NSMB05S50M1 - Footprint:
Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm - 3D model: SOP-23 (KiCad packages3D, STEP)
- 3D model files:
nsmb05s50m1-etched.step/nsmb05s50m1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nsmb05s50m1.step/nsmb05s50m1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WXNSIC datasheet (9 pp, sha256
0810b250857de45b, retrieved 2026-10-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NSMB05S50M1
**WXNSIC** · Intelligent Power Modules (IPM) · SOP-23
NSMB05S50M1 from WXNSIC, in a SOP-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COM | power_in | IC common supply ground. |
| 2 | VB(U) | power_in | Bias voltage for U-phase high-side MOSFET driving; VBS rated 20 V max, 10 to 18.5 V recommended. |
| 3 | VCC(U) | power_in | Bias voltage for U-phase IC and low-side MOSFET driving; VCC rated 20 V max, 10 to 18.5 V recommended. |
| 4 | IN(UH) | input | Signal input for U-phase high-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 5 | IN(UL) | input | Signal input for U-phase low-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 6 | N.C | unconnected | No connection. |
| 7 | VB(V) | power_in | Bias voltage for V-phase high-side MOSFET driving; VBS rated 20 V max, 10 to 18.5 V recommended. |
| 8 | VCC(V) | power_in | Bias voltage for V-phase IC and low-side MOSFET driving; VCC rated 20 V max, 10 to 18.5 V recommended. |
| 9 | IN(VH) | input | Signal input for V-phase high-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 10 | IN(VL) | input | Signal input for V-phase low-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 11 | VTS | output | Output for HVIC temperature sensing; 320 to 900 mV (typ 650 mV) at VCC = 15 V, THVIC = 25 °C. |
| 12 | VB(W) | power_in | Bias voltage for W-phase high-side MOSFET driving; VBS rated 20 V max, 10 to 18.5 V recommended. |
| 13 | VCC(W) | power_in | Bias voltage for W-phase IC and low-side MOSFET driving; VCC rated 20 V max, 10 to 18.5 V recommended. |
| 14 | IN(WH) | input | Signal input for W-phase high-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 15 | IN(WL) | input | Signal input for W-phase low-side, active high; ON threshold min 3.0 V, OFF threshold max 0.6 V. |
| 16 | N.C | unconnected | No connection. |
| 17 | P | power_in | Positive DC-link input; supply voltage VPN recommended 300 V typ, 400 V max, MOSFET VDSS 500 V. |
| 18 | U,VS(U) | power_out | Output for U-phase and bias voltage ground for high-side MOSFET driving. |
| 19 | NU | passive | Negative DC-link input for U-phase (low-side current sense terminal). |
| 20 | NV | passive | Negative DC-link input for V-phase (low-side current sense terminal). |
| 21 | V,VS(V) | power_out | Output for V-phase and bias voltage ground for high-side MOSFET driving. |
| 22 | NW | passive | Negative DC-link input for W-phase (low-side current sense terminal). |
| 23 | W,VS(W) | power_out | Output for W-phase and bias voltage ground for high-side MOSFET driving. |
| 24 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WXNSIC |
| Package | SOP-23 |
| Category | Transistors/Thyristors |
| Pins | 24 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 500 | | | V | VGS= 0 V, ID = 250 uA | 6 |
| Zero Gate Voltage Drain Current | IDSS | | | 1 | uA | VGS = 0 V, VDS = 500 V | 6 |
| Static Drain-Source Turn-On Resistance | RDS(on) | | 1.8 | 2.4 | Ω | VCC = VBS = 15V, VIN = 5V, ID =2.5A | 6 |
| Drain-Source Diode Forward Voltage | VSD | | 0.9 | 1.4 | V | VCC = VBS = 15V, ID = -5.0A | 6 |
| Quiescent VCC Supply Current | IQCC | | 100 | 220 | uA | VCC = 15V, VIN= 0V, between VCC and COM | 6 |
| Quiescent VB Supply Current | IQBS | | 50 | 100 | uA | VBS = 15V, VIN = 0V | 6 |
| HVIC Temperature Sensing Voltage Output | VTS | 320 | 650 | 900 | mV | VCC = 15V, THVIC=25 oC | 6 |
| ON Threshold Voltage Logic HIGH Level | VIH | | | 2.6 | V | Applied between VIN and COM | 6 |
| OFF Threshold Voltage Logic LOW Level | VIL | 0.8 | | | V | Applied between VIN and COM | 6 |
| Supply Voltage | VPN | | 300 | 400 | V | Applied between P and N | 5 |
| Control Supply Voltage | VCC | 10 | | 18.5 | V | Applied between VCC and COM | 5 |
| High-Side Bias Voltage | VBS | 10 | | 18.5 | V | Applied between VB and VS | 5 |
| Input ON Threshold Voltage | VIN(ON) | 3 | | | V | Applied between VIN and COM (max VCC) | 5 |
| Input OFF Threshold Voltage | VIN(OFF) | 0 | | 0.6 | V | Applied between VIN and COM | 5 |
| Drain-Source Voltage of Each MOSFET | VDSS | | | 500 | V | | 5 |
| Drain Current, Continuous | ID | | | 5 | A | TC = 25°C | 5 |
| Drain Pulse Current, Peak | IDP | | | 10 | A | TC = 25°C, Less than 100us | 5 |
| Drain Current, Rms | IDRMS | | | 0.6 | Arms | TC = 80°C, FPWM <20KHz | 5 |
| Maximum Power Dissipation | PD | | | 14 | W | TC = 25°C For each MOSFET | 5 |
| Control Supply Voltage | VCC | | | 20 | V | Applied between VCC and COM | 5 |
| High-side Bias Voltage | VBS | | | 20 | V | Applied between VB and VS | 5 |
| Bootstrap Max Repetitive Reverse Voltage | VRRMB | | | 500 | V | | 5 |
| Bootstrap Forward Current | IFB | | | 0.25 | A | TC = 25°C | 5 |
| Bootstrap Forward Peak Current | IFPB | | | 0.5 | A | TC = 25°C,Under 1ms Pulse Width | 5 |
| Operating Junction Temperature | TJ | -40 | | 150 | °C | | 5 |
| Storage Temperature | TSTG | -40 | | 150 | °C | | 5 |
| Isolation Voltage | VISO | | | 1500 | Vrms | 60Hz, Sinusoidal, 1 minute, Connect Pins to Heat-Sink Plate | 5 |
| Junction to Case Thermal Resistance | RθJC | | | 7.1 | °C/W | Each MOSFET under Inverter Operating Condition | 5 |
| Turn-on Time | tON | | 960 | | ns | VPN = 300 V, VCC = VBS = 15 V, ID = 0.5A, IN = 0V↔5V, L = 3 mH | 6 |
| Turn-off Time | tOFF | | 560 | | ns | VPN = 300 V, VCC = VBS = 15 V, ID = 0.5A, IN = 0V↔5V, L = 3 mH | 6 |
| Reverse Recovery Time | trr | | 230 | | ns | VPN = 300 V, VCC = VBS = 15 V, ID = 0.5A, IN = 0V↔5V, L = 3 mH | 6 |
| Low-side UVLO Detection Level | VCCD | | 7.7 | | V | | 6 |
| Low-side UVLO Reset Level | VCCR | | 8.7 | | V | | 6 |
| High-side UVLO Detection Level | VBSD | | 7.7 | | V | | 6 |
| High-side UVLO Reset Level | VBSR | | 8.7 | | V | | 6 |
| Bootstrap Diode Forward Voltage | VF BSD | | 2.8 | | V | IF = 0.1 A, TC = 25°C | 6 |
| Bootstrap Diode Reverse Recovery Time | trrB | | 80 | | ns | IF = 0.1 A, TC = 25°C | 6 |
| Bootstrap Current Limiting Resistor | R BSD | | 18 | | ohm | | 6 |
## CAD (KiCad official)
- Symbol: `NSMB05S50M1`
- Footprint: `Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm`
- 3D model: SOP-23 (KiCad packages3D, STEP)
- 3D model files: `nsmb05s50m1-etched.step` / `nsmb05s50m1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nsmb05s50m1.step` / `nsmb05s50m1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [WXNSIC datasheet](docs/nsmb05s50m1-datasheet.pdf) (9 pp, sha256 `0810b250857de45b`, retrieved 2026-10-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/nsmb05s50m1-datasheet.pdf)