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NSI8222N0-DSPR

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NOVOSENSE Digital Isolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NSI8222N0-DSPR

NOVOSENSE · Digital Isolators · SOP-8

NSI8222N0-DSPR from NOVOSENSE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1, with a recommended supply range of 2.5 V to 5.5 V and an absolute maximum of 6.5 V.
2 INA input Logic input A, with VIH of 2 V minimum and VIL of 0.8 V maximum, and an input voltage limit of VDD+0.4 V that must not exceed 6.5 V.
3 OUTB output Logic output B, with output current limited to -15 mA to 15 mA and an output voltage limit of VDD+0.4 V that must not exceed 6.5 V.
4 GND1 power_in Ground 1, the ground reference for isolator side 1.
5 GND2 power_in Ground 2, the ground reference for isolator side 2.
6 INB input Logic input B, with VIH of 2 V minimum and VIL of 0.8 V maximum, and an input voltage limit of VDD+0.4 V that must not exceed 6.5 V.
7 OUTA output Logic output A, with output current limited to -15 mA to 15 mA and an output voltage limit of VDD+0.4 V that must not exceed 6.5 V.
8 VDD2 power_in Power supply for isolator side 2, with a recommended supply range of 2.5 V to 5.5 V and an absolute maximum of 6.5 V.

Key specifications

Parameter Value
Manufacturer NOVOSENSE
Package SOP-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power on Reset threshold VDDPOR 2.2 V POR threshold as during power-up 10
POR threshold hysteresis VDD HYS 0.1 V POR threshold hysteresis 10
High Level Input Voltage VIH 2 V 10
Low Level Input Voltage VIL 0.8 V 10
Low Level Output Voltage VOL 0.4 V IOL ≤ 4mA 10
Output Impedance Rout 50 ohm 10
Input pull high or low current Ipull 8 15 uA 10
Start Up Time after POR trbs 10 usec 10
Common Mode Transient Immunity CMTI -200 250 kV/us See Figure 5.8 10
Power Supply Voltage VDD1, VDD2 2.5 5.5 V 9
Operating Temperature Topr -55 125 ℃ 9
High Level Input Voltage (recommended) VIH 2 V 9
Low Level Input Voltage (recommended) VIL 0.8 V 9
Data rate DR 150 Mbps 9
Power Supply Voltage VDD1, VDD2 -0.5 6.5 V 9
Maximum Input Voltage VINA, VINB -0.4 V Max printed as VDD+0.4 V; the maximum voltage must not exceed 6.5V 9
Maximum Output Voltage VOUTA, VOUTB -0.4 V Max printed as VDD+0.4 V; the maximum voltage must not exceed 6.5V 9
Maximum Input/Output Pulse Voltage VINA, VINB, VOUTA, VOUTB -0.8 V Max printed as VDD+0.8 V; pulse width less than 100ns, duty cycle less than 10% 9
Output current Io -15 15 mA 9
Operating Temperature Topr -55 125 ℃ 9
Junction Temperature Tj 150 ℃ 9
Storage Temperature Tstg -65 150 ℃ 9
Electrostatic discharge HBM HBM -8000 8000 V 9
Electrostatic discharge CDM CDM -2000 2000 V 9
IC Junction-to-Air Thermal Resistance (SOP8) θJA 137.7 ℃/W SOP8 package 10
Junction-to-case (top) thermal resistance (SOP8) θJC（top） 54.9 ℃/W SOP8 package 10
Junction-to-board thermal resistance (SOP8) θJB 71.7 ℃/W SOP8 package 10
IDD1 quiescent (Q0) IDD1(Q0) 0.94 1.41 mA VDD=5V; All Input 0V for NSi822xx0 Or All Input at supply for NSi822xx1 11
IDD2 quiescent (Q0) IDD2(Q0) 0.94 1.41 mA VDD=5V; All Input 0V for NSi822xx0 Or All Input at supply for NSi822xx1 11
IDD1 quiescent (Q1) IDD1(Q1) 2.06 3.09 mA VDD=5V; All Input at supply for NSi822xx0 Or All Input 0V for NSi822xx1 11
IDD2 quiescent (Q1) IDD2(Q1) 2.06 3.09 mA VDD=5V; All Input at supply for NSi822xx0 Or All Input 0V for NSi822xx1 11
IDD1 at 1 Mbps IDD1(1M) 1.55 2.32 mA VDD=5V; All Input with 1Mbps, CL=15pF 11
IDD2 at 1 Mbps IDD2(1M) 1.55 2.32 mA VDD=5V; All Input with 1Mbps, CL=15pF 11
IDD1 at 10 Mbps IDD1(10M) 1.96 2.93 mA VDD=5V; All Input with 10Mbps, CL=15pF 11
IDD2 at 10 Mbps IDD2(10M) 1.96 2.93 mA VDD=5V; All Input with 10Mbps, CL=15pF 11
IDD1 at 100 Mbps IDD1(100M) 5.86 10.05 mA VDD=5V; All Input with 100Mbps, CL = 15pF 11
IDD2 at 100 Mbps IDD2(100M) 5.86 10.05 mA VDD=5V; All Input with 100Mbps, CL = 15pF 11
Data Rate DR 0 150 Mbps 5V supply 14
Minimum Pulse Width PW 5 ns 5V supply 14
Propagation Delay (low-to-high) tPLH 2.5 6.54 15 ns See Figure 5.7, CL = 15pF 14
Propagation Delay (high-to-low) tPHL 2.5 8.3 15 ns See Figure 5.7, CL = 15pF 14
Pulse Width Distortion PWD 5 ns /tPHL, tPLH/; See Figure 5.7, CL = 15pF 14
Rising Time tr 5 ns See Figure 5.7, CL = 15pF 14
Falling Time tf 5 ns See Figure 5.7, CL = 15pF 14
Peak Eye Diagram Jitter tJIT(PK) 350 ps 14
Channel-to-Channel Delay Skew tSK(c2c) 2.5 ns 14
Part-to-Part Delay Skew tSK(p2p) 5 ns 14

CAD (KiCad official)

  • Symbol: NSI8222N0-DSPR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: nsi8222n0-dspr-etched.step / nsi8222n0-dspr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsi8222n0-dspr.step / nsi8222n0-dspr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NOVOSENSE datasheet (41 pp, sha256 6c904c0e109fd57e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF