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NSI8221N0-DSPR

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NOVOSENSE Digital Isolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NSI8221N0-DSPR

NOVOSENSE · Digital Isolators · SOP-8

NSI8221N0-DSPR from NOVOSENSE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1, specified from 2.5V to 5.5V, with a 0.1 µF bypass capacitor required between VDD1 and GND1 placed as close to the package as possible.
2 OUTA output Logic output A (side 2), with VOH of at least VDD2 − 0.4V at IOH ≤ 4mA and VOL of at most 0.4V at IOL ≤ 4mA, and typical output impedance of about 50 Ω ±40%.
3 INB input Logic input B (side 1), with VIH minimum 2V and VIL maximum 0.8V, and input voltage not to exceed VDD + 0.4V (absolute maximum 6.5V).
4 GND1 power_in Ground 1, the ground reference for isolator side 1 and the return for the VDD1 bypass capacitor.
5 GND2 power_in Ground 2, the ground reference for isolator side 2 and the return for the VDD2 bypass capacitor.
6 OUTB output Logic output B (side 1), with VOH of at least VDD1 − 0.4V at IOH ≤ 4mA and VOL of at most 0.4V at IOL ≤ 4mA, and typical output impedance of about 50 Ω ±40%.
7 INA input Logic input A (side 2), with VIH minimum 2V and VIL maximum 0.8V, and input voltage not to exceed VDD + 0.4V (absolute maximum 6.5V).
8 VDD2 power_in Power supply for isolator side 2, specified from 2.5V to 5.5V, with a 0.1 µF bypass capacitor required between VDD2 and GND2 placed as close to the package as possible.

Key specifications

Parameter Value
Manufacturer NOVOSENSE
Package SOP-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VDD1, VDD2 -0.5 6.5 V 6
Maximum Input Voltage VINA, VINB -0.4 V The maximum voltage must not exceed 6.5V 6
Maximum Output Voltage VOUTA, VOUTB -0.4 V The maximum voltage must not exceed 6.5V 6
Maximum Input/Output Pulse Voltage VINA, VINB, VOUTA, VOUTB -0.8 V Pulse width should be less than 100ns, and the duty cycle should be less than 10% 6
Output current Io -15 15 mA 6
Operating Temperature Topr -40 125 ℃ 6
Junction temperature Tj -40 150 ℃ 6
Storage Temperature Tstg -40 150 ℃ 6
Electrostatic discharge HBM -8000 8000 V 6
Electrostatic discharge CDM -2000 2000 V 7
Power Supply Voltage VDD1, VDD2 2.5 5.5 V 7
Operating Temperature Topr -40 125 ℃ 7
High Level Input Voltage VIH 2 V 7
Low Level Input Voltage VIL 0.8 V 7
Data rate DR 150 Mbps 7
Low Level Output Voltage VOL 0.4 V IOL ≤ 4mA 8
Input Pull high or low Current Ipull 8 15 uA 8
Start Up Time after POR trbs 10 usec 8
Common Mode Transient Immunity CMTI 200 250 kV/us See Figure 5.8 8
Supply current IDD1 Q0 (5V, NSi8221/NSi8222) IDD1(Q0) 0.94 1.41 mA All Input 0V for NSi822xx0 Or All Input at supply for NSi822xx1 9
Supply current IDD2 Q0 (5V, NSi8221/NSi8222) IDD2(Q0) 0.94 1.41 mA 9
Supply current IDD1 Q1 (5V, NSi8221/NSi8222) IDD1(Q1) 2.06 3.09 mA All Input at supply for NSi822xx0 Or All Input 0V for NSi822xx1 9
Supply current IDD2 Q1 (5V, NSi8221/NSi8222) IDD2(Q1) 2.06 3.09 mA 9
Supply current IDD1 at 1Mbps (5V, NSi8221/NSi8222) IDD1(1M) 1.55 2.32 mA All Input with 1Mbps, CL=15pF 9
Supply current IDD2 at 1Mbps (5V, NSi8221/NSi8222) IDD2(1M) 1.55 2.32 mA 9
Supply current IDD1 at 10Mbps (5V, NSi8221/NSi8222) IDD1(10M) 1.96 2.93 mA All Input with 10Mbps, CL=15pF 9
Supply current IDD2 at 10Mbps (5V, NSi8221/NSi8222) IDD2(10M) 1.96 2.93 mA 9
Supply current IDD1 at 100Mbps (5V, NSi8221/NSi8222) IDD1(100M) 5.86 8.78 mA All Input with 100Mbps, CL = 15pF 9
Supply current IDD2 at 100Mbps (5V, NSi8221/NSi8222) IDD2(100M) 5.86 8.78 mA 9
Data Rate (5V supply) DR 0 150 Mbps 11
Minimum Pulse Width (5V supply) PW 5 ns 11
Propagation Delay low-to-high (5V supply) tPLH 2.5 6.54 15 ns See Figure 5.7, CL = 15pF 11
Propagation Delay high-to-low (5V supply) tPHL 2.5 8.3 15 ns See Figure 5.7, CL = 15pF 11
Pulse Width Distortion /tPHL, tPLH/ (5V supply) PWD 5 ns See Figure 5.7, CL = 15pF 11
Rising Time (5V supply) tr 5 ns See Figure 5.7, CL = 15pF 11
Falling Time (5V supply) tf 5 ns See Figure 5.7, CL = 15pF 11
Peak Eye Diagram Jitter (5V supply) tJIT(PK) 350 ps 11
Channel-to-Channel Delay Skew (5V supply) tSK(c2c) 2.5 ns 11
Part-to-Part Delay Skew (5V supply) tSK(p2p) 5 ns 11
Data Rate (3.3V supply) DR 0 150 Mbps 12
Minimum Pulse Width (3.3V supply) PW 5 ns 12
Propagation Delay low-to-high (3.3V supply) tPLH 2.5 8 15 ns See Figure 5.7, CL = 15pF 12
Propagation Delay high-to-low (3.3V supply) tPHL 2.5 8.7 15 ns See Figure 5.7, CL = 15pF 12
Pulse Width Distortion /tPHL, tPLH/ (3.3V supply) PWD 5 ns See Figure 5.7, CL = 15pF 12
Rising Time (3.3V supply) tr 5 ns See Figure 5.7, CL = 15pF 12
Falling Time (3.3V supply) tf 5 ns See Figure 5.7, CL = 15pF 12
Peak Eye Diagram Jitter (3.3V supply) tJIT(PK) 350 ps 12
Channel-to-Channel Delay Skew (3.3V supply) tSK(c2c) 2.5 ns 12
Part-to-Part Delay Skew (3.3V supply) tSK(p2p) 5 ns 12
Junction-to-Air Thermal Resistance (SOP8) θJA 137.7 ℃/W 7
Junction-to-case (top) thermal resistance (SOP8) θJC(top) 54.9 ℃/W 7
Junction-to-board thermal resistance (SOP8) θJB 71.7 ℃/W 7
Power on Reset threshold VDDPOR 2.2 V POR threshold as during power-up 8
POR threshold Hysteresis VDD HYS 0.1 V POR threshold Hysteresis 8
Input Threshold at rising edge VIT 1.6 V Input Threshold at rising edge 8
Input Threshold Hysteresis VIT_HYS 0.4 V Input Threshold Hysteresis 8
Output Impedance Rout 50 ohm 8

CAD (KiCad official)

  • Symbol: NSI8221N0-DSPR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: nsi8221n0-dspr-etched.step / nsi8221n0-dspr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsi8221n0-dspr.step / nsi8221n0-dspr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NOVOSENSE datasheet (31 pp, sha256 a44b95fb4fbf6bb2, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF