component
NSI8220N0-DSPR
Public Made by Adomby adom
NOVOSENSE Digital Isolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 4h ago |
| viewers | 4h ago |
| nsi8220n0-dspr-etched.glb | 4h ago |
| nsi8220n0-dspr-etched.step | 4h ago |
| nsi8220n0-dspr-hero.glb | 4h ago |
| nsi8220n0-dspr-hero.overlay.json | 4h ago |
| nsi8220n0-dspr.glb | 4h ago |
| nsi8220n0-dspr.kicad_mod | 4h ago |
| nsi8220n0-dspr.kicad_sym | 4h ago |
| nsi8220n0-dspr.lbr | 4h ago |
| nsi8220n0-dspr.step | 4h ago |
| package.json | 4h ago |
| page.json | 4h ago |
| README.md | 4h ago |
NSI8220N0-DSPR
NOVOSENSE · Digital Isolators · SOP-8
NSI8220N0-DSPR from NOVOSENSE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for isolator side 1, with a recommended operating range of 2.5V to 5.5V and a 0.1 µF bypass capacitor required between VDD1 and GND1. |
| 2 | INA | input | Logic input A, with a high level input voltage (VIH) of at least 2V and a low level input voltage (VIL) of at most 0.8V. |
| 3 | INB | input | Logic input B, with a high level input voltage (VIH) of at least 2V and a low level input voltage (VIL) of at most 0.8V. |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | OUTB | output | Logic output B, with a high level output voltage (VOH) of VDD-0.4V at IOH ≤ 4mA and a low level output voltage (VOL) of at most 0.4V at IOL ≤ 4mA. |
| 7 | OUTA | output | Logic output A, with a high level output voltage (VOH) of VDD-0.4V at IOH ≤ 4mA and a low level output voltage (VOL) of at most 0.4V at IOL ≤ 4mA. |
| 8 | VDD2 | power_in | Power supply for isolator side 2, with a recommended operating range of 2.5V to 5.5V and a 0.1 µF bypass capacitor required between VDD2 and GND2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | SOP-8 |
| Category | Interface ICs |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
NSI8220N0-DSPR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
nsi8220n0-dspr-etched.step/nsi8220n0-dspr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nsi8220n0-dspr.step/nsi8220n0-dspr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NOVOSENSE datasheet (31 pp, sha256
a44b95fb4fbf6bb2, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).