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NSI8210N1-Q1SPR
Public Made by Adomby adom
NOVOSENSE Digital Isolators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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NSI8210N1-Q1SPR
NOVOSENSE · Digital Isolators · SOP-8
NSI8210N1-Q1SPR from NOVOSENSE, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for isolator side 1; recommended supply range is 2.5V to 5.5V, with a 0.1 µF bypass capacitor between VDD1 and GND1 placed as close to the package as possible. |
| 2 | IN | input | Logic input to side 1; VIH minimum 2V and VIL maximum 0.8V. |
| 3 | VDD1 | power_in | Power supply for isolator side 1; recommended supply range is 2.5V to 5.5V, with a 0.1 µF bypass capacitor between VDD1 and GND1 placed as close to the package as possible. |
| 4 | GND1 | power_in | Ground reference for isolator side 1 (input side). |
| 5 | GND2 | power_in | Ground reference for isolator side 2 (output side). |
| 6 | OUT | output | Logic output from side 2; VOH is VDD-0.4V minimum at IOH=-4mA and VOL is 0.4V maximum at IOL=4mA, with absolute output voltage not to exceed 6.5V. |
| 7 | NC | unconnected | Not connected; no internal connection. |
| 8 | VDD2 | power_in | Power supply for isolator side 2; recommended supply range is 2.5V to 5.5V, with a 0.1 µF bypass capacitor between VDD2 and GND2 placed as close to the package as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | SOP-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage | VDD1, VDD2 | 2.5 | 5.5 | V | 6 | ||
| Data Rate | DR | 0 | 150 | Mbps | 6 | ||
| Ambient Temperature | Ta | -40 | 125 | ℃ | 6 | ||
| High-level Input Voltage | VIH | 2 | V | 6 | |||
| Low-level Input Voltage | VIL | 0.8 | V | 6 | |||
| Power Supply Voltage | VDD1, VDD2 | -0.5 | 6.5 | V | 6 | ||
| Maximum Input Voltage | IN | -0.4 | V | The maximum voltage must not exceed 6.5V | 6 | ||
| Maximum Output Voltage | OUT | -0.4 | V | The maximum voltage must not exceed 6.5V | 6 | ||
| Maximum Input/Output Pulse Voltage | IN, OUT | -0.8 | V | Pulse width should be less than 100ns, and the duty cycle should be less than 10% | 6 | ||
| Output current | Io | -15 | 15 | mA | 6 | ||
| Maximum Surge Isolation Voltage | VIOSM | 6.25 | kV | VTEST=VIOSM×1.6 | 6 | ||
| Operating Temperature | Topr | -40 | 125 | ℃ | 6 | ||
| Junction Temperature | Tj | -40 | 150 | ℃ | 6 | ||
| Storage Temperature | Tstg | -65 | 150 | ℃ | 6 | ||
| Electrostatic discharge HBM | HBM | -8000 | 8000 | V | 6 | ||
| Electrostatic discharge CDM | CDM | -2000 | 2000 | V | 6 | ||
| High Level Input Voltage | VIH | 2 | V | 7 | |||
| Low Level Input Voltage | VIL | 0.8 | V | 7 | |||
| Low Level Output Voltage | VOL | 0.4 | V | IOL = 4mA | 7 | ||
| Input Pull high or low Current | Ipull | 8 | 15 | uA | 7 | ||
| Common Mode Transient Immunity | CMTI | 200 | 250 | kV/us | See Figure 5.6, CL = 15pF | 7 | |
| Minimum Pulse Width | PW | 5 | ns | 9 | |||
| Propagation Delay tPLH (5V) | tPLH | 2.5 | 6.54 | 15 | ns | See Figure 5.5, CL = 15pF | 9 |
| Propagation Delay tPHL (5V) | tPHL | 2.5 | 8.3 | 15 | ns | See Figure 5.5, CL = 15pF | 9 |
| Pulse Width Distortion (5V) | PWD | 5 | ns | See Figure 5.5, CL = 15pF | 9 | ||
| Rising Time (5V) | tr | 5 | ns | See Figure 5.5, CL = 15pF | 9 | ||
| Falling Time (5V) | tf | 5 | ns | See Figure 5.5, CL = 15pF | 9 | ||
| Peak Eye Diagram Jitter (5V) | tJIT(PK) | 350 | ps | 9 | |||
| Channel-to-Channel Delay Skew (5V) | tSK(c2c) | 2.5 | ns | 9 | |||
| Part-to-Part Delay Skew (5V) | tSK(p2p) | 5 | ns | 9 | |||
| Minimum Pulse Width | PW | 5 | ns | 10 | |||
| Propagation Delay tPLH (3.3V) | tPLH | 2.5 | 8 | 15 | ns | See Figure 5.5, CL = 15pF | 10 |
| Propagation Delay tPHL (3.3V) | tPHL | 2.5 | 8.7 | 15 | ns | See Figure 5.5, CL = 15pF | 10 |
| Pulse Width Distortion (3.3V) | PWD | 5 | ns | See Figure 5.5, CL = 15pF | 10 | ||
| Rising Time (3.3V) | tr | 5 | ns | See Figure 5.5, CL = 15pF | 10 | ||
| Falling Time (3.3V) | tf | 5 | ns | See Figure 5.5, CL = 15pF | 10 | ||
| Peak Eye Diagram Jitter (3.3V) | tJIT(PK) | 350 | ps | 10 | |||
| Channel-to-Channel Delay Skew (3.3V) | tSK(c2c) | 2.5 | ns | 10 | |||
| Part-to-Part Delay Skew (3.3V) | tSK(p2p) | 5 | ns | 10 | |||
| Minimum Pulse Width | PW | 5 | ns | 11 | |||
| Pulse Width Distortion (2.5V) | PWD | 5 | ns | See Figure 5.5, CL = 15pF | 11 | ||
| Rising Time (2.5V) | tr | 5 | ns | See Figure 5.5, CL = 15pF | 11 | ||
| Falling Time (2.5V) | tf | 5 | ns | See Figure 5.5, CL = 15pF | 11 | ||
| Channel-to-Channel Delay Skew (2.5V) | tSK(c2c) | 2.5 | ns | 11 | |||
| Part-to-Part Delay Skew (2.5V) | tSK(p2p) | 5 | ns | 11 | |||
| Supply current VDD1 (Q0) | IDD1(Q0) | 0.64 | 0.96 | mA | All Input at supply for NSi8210N1 | 8 | |
| Supply current VDD2 (Q0) | IDD2(Q0) | 1.27 | 1.91 | mA | 8 | ||
| Supply current VDD1 (Q1) | IDD1(Q1) | 1.66 | 2.49 | mA | All Input 0V for NSi8210N1 | 8 | |
| Supply current VDD2 (Q1) | IDD2(Q1) | 1.28 | 1.92 | mA | 8 | ||
| Power on Reset | VDDPOR | 2.2 | V | POR threshold as during power-up | 7 | ||
| POR threshold Hysteresis | VDD HYS | 0.1 | V | POR threshold Hysteresis | 7 | ||
| Input Threshold | VIT | 1.6 | V | Input Threshold at rising edge | 7 | ||
| Input Threshold Hysteresis | VIT_HYS | 0.4 | V | Input Threshold Hysteresis | 7 | ||
| Start Up Time after POR | trbs | 10 | usec | 7 | |||
| IC Junction-to-Air Thermal Resistance (SOP8) | θJA | 146.1 | °C/W | 7 | |||
| Junction-to-case (top) thermal resistance (SOP8) | θJC(top) | 63.1 | °C/W | 7 | |||
| Junction-to-board thermal resistance (SOP8) | θJB | 80 | °C/W | 7 |
CAD (KiCad official)
- Symbol:
NSI8210N1-Q1SPR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
nsi8210n1-q1spr-etched.step/nsi8210n1-q1spr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nsi8210n1-q1spr.step/nsi8210n1-q1spr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NOVOSENSE datasheet (32 pp, sha256
5e9c56a292e239a6, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).