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NSI8141W1

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NOVOSENSE Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NSI8141W1

NOVOSENSE · Digital Isolators · SOIC-16-300mil

NSI8141W1 from NOVOSENSE, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1, specified for 2.5V to 5.5V operation.
2 GND1 power_in Ground 1, the ground reference for isolator side 1.
3 INA input Logic input A for side 1.
4 INB input Logic input B for side 1.
5 INC input Logic input C for side 1.
6 OUTD output Logic output D; the typical output impedance is approximately 50 Ω ±40% per Section 5.1.
7 NC/EN1 input No connection, or output enable 1: when EN1 is high or NC the side-1 outputs are enabled, and when EN1 is low they are disabled to high impedance.
8 GND1 power_in Ground 1, the ground reference for isolator side 1.
9 GND2 power_in Ground 2, the ground reference for isolator side 2.
10 EN2 input Output enable 2, active high: when EN2 is high or NC the side-2 outputs are enabled, and when EN2 is low they are disabled to high impedance.
11 IND input Logic input D.
12 OUTC output Logic output C.
13 OUTB output Logic output B.
14 OUTA output Logic output A.
15 GND2 power_in Ground 2, the ground reference for isolator side 2.
16 VDD2 power_in Power supply for isolator side 2, specified for 2.5V to 5.5V operation.

Key specifications

Parameter Value
Manufacturer NOVOSENSE
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VDD1, VDD2 -0.5 6.5 V 3
Maximum Input Voltage VINA, VINB, VINC, VIND -0.4 V 3
Maximum Output Voltage VOUTA, VOUTB, VOUTC -0.4 V 3
Maximum Input/Output Pulse Voltage VINA, VINB, VINC, VOUTA, VOUTB, VOUTC -0.8 V Pulse width less than 100ns, duty cycle less than 10% 3
Common-Mode Transients CMTI -150 150 kV/us 3
Output current Io -15 15 mA 3
Maximum Surge Isolation Voltage VIOSM 5.3 kV 3
Operating Temperature Topr -40 125 ℃ 3
Storage Temperature Tstg -40 150 ℃ 3
Electrostatic discharge HBM HBM -6000 6000 V 3
Electrostatic discharge CDM CDM -2000 2000 V 3
Power Supply Voltage side 1 (electrical characteristics range) VDD1 2.5 5.5 V Electrical characteristics header: VDD1=2.5V~5.5V, Ta=-40℃ to 125℃ 3
Power Supply Voltage side 2 (electrical characteristics range) VDD2 2.5 5.5 V Electrical characteristics header: VDD2=2.5V~5.5V, Ta=-40℃ to 125℃ 3
High Level Input Voltage VIH 2 V 3
Low Level Input Voltage VIL 0.8 V 3
Low Level Output Voltage VOL 0.3 V IOL = 4mA 3
Data Rate DR 0 150 Mbps VDD1=5V±10%, VDD2=5V±10%, Ta=-40℃ to 125℃ 5
Minimum Pulse Width PW 5 ns VDD1=5V±10%, VDD2=5V±10%, Ta=-40℃ to 125℃ 5
Propagation Delay rising tPLH 5 8.2 15 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.9, CL = 15pF 5
Propagation Delay falling tPHL 5 10.56 15 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.9, CL = 15pF 5
Pulse Width Distortion /tPHL, tPLH/ 5 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.9, CL = 15pF 5
Rising Time tr 5 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.9, CL = 15pF 5
Falling Time tf 5 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.9, CL = 15pF 5
Peak Eye Diagram Jitter tJIT(PK) 350 ps VDD1=5V±10%, VDD2=5V±10% 5
Channel-to-Channel Delay Skew tSK(c2c) 2.5 ns VDD1=5V±10%, VDD2=5V±10% 5
Part-to-Part Delay Skew tSK(p2p) 5 ns VDD1=5V±10%, VDD2=5V±10% 5
Disable high to Tri-State tPHZ 14.88 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.10, CL = 15pF, RL=1k 5
Enable to Data high Valid tPZH 10 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.10, CL = 15pF, RL=1k 5
Disable low to Tri-State tPLZ 17.25 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.10, CL = 15pF, RL=1k 5
Enable to Data low Valid tPZL 10.85 ns VDD1=5V±10%, VDD2=5V±10%; See Figure 2.10, CL = 15pF, RL=1k 5
Supply current VDD1 Q0 (quiescent, NSi8141x1) IDD1(Q0) 1.244 1.87 mA VDD1=5V±10%, VDD2=5V±10%; All Input 0V for NSi8141x0 Or All Input at supply for NSi8141x1 4
Supply current VDD2 Q0 (quiescent, NSi8141x1) IDD2(Q0) 2.164 3.25 mA VDD1=5V±10%, VDD2=5V±10%; All Input 0V for NSi8141x0 Or All Input at supply for NSi8141x1 4
Supply current VDD1 Q1 (NSi8141x1) IDD1(Q1) 4.658 7 mA VDD1=5V±10%, VDD2=5V±10%; All Input at supply for NSi8141x0 Or All Input 0V for NSi8141x1 4
Supply current VDD2 Q1 (NSi8141x1) IDD2(Q1) 3.416 5 mA VDD1=5V±10%, VDD2=5V±10%; All Input at supply for NSi8141x0 Or All Input 0V for NSi8141x1 4
Supply current VDD1 at 1Mbps IDD1(1M) 3.07 4.6 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 1Mbps, CL=15pF 4
Supply current VDD2 at 1Mbps IDD2(1M) 3.064 4.6 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 1Mbps, CL=15pF 4
Supply current VDD1 at 10Mbps IDD1(10M) 3.82 5.7 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 10Mbps, CL=15pF 4
Supply current VDD2 at 10Mbps IDD2(10M) 5.496 8.2 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 10Mbps, CL=15pF 4
Supply current VDD1 at 100Mbps IDD1(100M) 10.708 16.06 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 100Mbps, CL = 15pF 4
Supply current VDD2 at 100Mbps IDD2(100M) 29.336 44 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 100Mbps, CL = 15pF 4
Supply current VDD1 Q0 (quiescent, NSi8141x1) IDD1(Q0) 1.165 1.75 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input 0V for NSi8141x0 Or All Input at supply for NSi8141x1 6
Supply current VDD2 Q0 (quiescent, NSi8141x1) IDD2(Q0) 2.062 3.1 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input 0V for NSi8141x0 Or All Input at supply for NSi8141x1 6
Supply current VDD1 Q1 (NSi8141x1) IDD1(Q1) 4.566 6.85 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input at supply for NSi8141x0 Or All Input 0V for NSi8141x1 6
Supply current VDD2 Q1 (NSi8141x1) IDD2(Q1) 3.306 5 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input at supply for NSi8141x0 Or All Input 0V for NSi8141x1 6
Supply current VDD1 at 1Mbps IDD1(1M) 2.954 4.4 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 1Mbps, CL=15pF 6
Supply current VDD2 at 1Mbps IDD2(1M) 2.862 4.3 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 1Mbps, CL=15pF 6
Supply current VDD1 at 10Mbps IDD1(10M) 3.452 5.2 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 10Mbps, CL=15pF 6
Supply current VDD2 at 10Mbps IDD2(10M) 4.368 6.5 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 10Mbps, CL=15pF 6
Supply current VDD1 at 100Mbps IDD1(100M) 8.084 12 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 100Mbps, CL = 15pF 6
Supply current VDD2 at 100Mbps IDD2(100M) 19.96 30 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 100Mbps, CL = 15pF 6
Supply current VDD1 Q0 (quiescent, NSi8141x1) IDD1(Q0) 1.128 1.7 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input 0V for NSi8141x0 Or All Input at supply for NSi8141x1 7
Supply current VDD2 Q0 (quiescent, NSi8141x1) IDD2(Q0) 2.012 3 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input 0V for NSi8141x0 Or All Input at supply for NSi8141x1 7
Supply current VDD1 Q1 (NSi8141x1) IDD1(Q1) 4.51 6.8 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input at supply for NSi8141x0 Or All Input 0V for NSi8141x1 7
Supply current VDD2 Q1 (NSi8141x1) IDD2(Q1) 3.248 4.9 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input at supply for NSi8141x0 Or All Input 0V for NSi8141x1 7
Supply current VDD1 at 1Mbps IDD1(1M) 2.894 4.3 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 1Mbps, CL=15pF 7
Supply current VDD2 at 1Mbps IDD2(1M) 2.766 4.15 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 1Mbps, CL=15pF 7
Supply current VDD1 at 10Mbps IDD1(10M) 3.272 4.9 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 10Mbps, CL=15pF 7
Supply current VDD2 at 10Mbps IDD2(10M) 3.892 5.8 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 10Mbps, CL=15pF 7
Supply current VDD1 at 100Mbps IDD1(100M) 6.95 10.4 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 100Mbps, CL = 15pF 8
Supply current VDD2 at 100Mbps IDD2(100M) 15.706 23.56 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 100Mbps, CL = 15pF 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-10, each NSi8140N/NSi8141N/NSi8142N is proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * 13

CAD (KiCad official)

  • Symbol: NSI8141W1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: nsi8141w1-etched.step / nsi8141w1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsi8141w1.step / nsi8141w1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NOVOSENSE datasheet (20 pp, sha256 65ebe98fcc7a575f, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF