# NSI8140N1

**NOVOSENSE** · Digital Isolators · SOIC-16

NSI8140N1 from NOVOSENSE, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for isolator side 1, specified at 2.5 V to 5.5 V and decoupled with a 0.1 µF bypass capacitor to GND1 placed as close to the package as possible. |
| 2 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 3 | INA | input | Logic input A, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 4 | INB | input | Logic input B, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 5 | INC | input | Logic input C, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 6 | IND | input | Logic input D, with VIH minimum 2 V and VIL maximum 0.8 V. |
| 7 | NC | input | No connection, or output enable 1; an active-high input where a high level or NC enables the side-1 outputs and a low level disables them to high impedance. |
| 8 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 10 | EN2 | input | Output enable 2; an active-high logic input where a high level or NC enables the side-2 outputs and a low level disables them to high impedance. |
| 11 | OUTD | output | Logic output D, with VOH of VDD−0.3 V at IOH = −4 mA and VOL of 0.3 V maximum at IOL = 4 mA. |
| 12 | OUTC | output | Logic output C, with VOH of VDD−0.3 V at IOH = −4 mA and VOL of 0.3 V maximum at IOL = 4 mA. |
| 13 | OUTB | output | Logic output B, with VOH of VDD−0.3 V at IOH = −4 mA and VOL of 0.3 V maximum at IOL = 4 mA. |
| 14 | OUTA | output | Logic output A, with VOH of VDD−0.3 V at IOH = −4 mA and VOL of 0.3 V maximum at IOL = 4 mA. |
| 15 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 16 | VDD2 | power_in | Power supply for isolator side 2, specified at 2.5 V to 5.5 V and decoupled with a 0.1 µF bypass capacitor to GND2 placed as close to the package as possible. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage | VDD1, VDD2 | -0.5 |  | 6.5 | V |  | 3 |
| Maximum Input Voltage | VINA,VINB, VINC, VIND | -0.4 |  |  | V |  | 3 |
| Maximum Output Voltage | VOUTA,VOUTB, VOUTC | -0.4 |  |  | V |  | 3 |
| Maximum Input/Output Pulse Voltage | VINA, VINB, VINC,VOUTA, VOUTB,VOUTC | -0.8 |  |  | V | Pulse width should be less than 100ns, and the duty cycle should be less than 10% | 3 |
| Output current | Io | -15 |  | 15 | mA |  | 3 |
| Maximum Surge Isolation Voltage | VIOSM |  |  | 5.3 | kV |  | 3 |
| Operating Temperature | Topr | -40 |  | 125 | ℃ |  | 3 |
| Storage Temperature | Tstg | -40 |  | 150 | ℃ |  | 3 |
| Common-Mode Transients | CMTI | -150 |  | 150 | kV/us |  | 3 |
| Electrostatic discharge HBM | HBM | -6000 |  | 6000 | V |  | 3 |
| Electrostatic discharge CDM | CDM | -2000 |  | 2000 | V |  | 3 |
| Power Supply Voltage | VDD1, VDD2 | 2.5 |  | 5.5 | V |  | 4 |
| Operating Temperature | Topr | -40 |  | 125 | ℃ |  | 4 |
| High Level Input Voltage | VIH | 2 |  |  | V |  | 4 |
| Low Level Input Voltage | VIL |  |  | 0.8 | V |  | 4 |
| Data rate | DR |  |  | 150 | Mbps |  | 4 |
| High Level Input Voltage | VIH | 2 |  |  | V |  | 4 |
| Low Level Input Voltage | VIL |  |  | 0.8 | V |  | 4 |
| Low Level Output Voltage | VOL |  |  | 0.3 | V | IOL = 4mA | 4 |
| Input Pull high or low Current | Ipull |  | 8 | 15 | uA |  | 4 |
| Common Mode Transient Immunity | CMTI | 100 | 150 |  | kV/us |  | 4 |
| Supply current (NSi8140) IDD1 | IDD1(Q0) |  | 0.894 | 1.5 | mA | All Input at supply for NSi8140x1 | 5 |
| Supply current (NSi8140) IDD2 | IDD2(Q0) |  | 2.326 | 3.5 | mA |  | 5 |
| Supply current (NSi8140) IDD1 | IDD1(Q1) |  | 5.316 | 7.8 | mA | All Input 0V for NSi8140x1 | 5 |
| Supply current (NSi8140) IDD2 | IDD2(Q1) |  | 2.432 | 3.65 | mA |  | 5 |
| Supply current (NSi8140) IDD1 | IDD1(1M) |  | 3.087 | 4.63 | mA | All Input with 1Mbps, CL=15pF | 5 |
| Supply current (NSi8140) IDD2 | IDD2(1M) |  | 2.728 | 4.09 | mA |  | 5 |
| Supply current (NSi8140) IDD1 | IDD1(10M) |  | 3.182 | 4.77 | mA | All Input with 10Mbps, CL=15pF | 5 |
| Supply current (NSi8140) IDD2 | IDD2(10M) |  | 5.834 | 8.75 | mA |  | 5 |
| Supply current (NSi8140) IDD1 | IDD1(100M) |  | 3.918 | 5.88 | mA | All Input with 100Mbps, CL=15pF | 5 |
| Supply current (NSi8140) IDD2 | IDD2(100M) |  | 37.06 | 55.6 | mA |  | 5 |
| Minimum Pulse Width | PW | 5 |  |  | ns |  | 6 |
| Propagation Delay | tPLH | 5 | 8.2 | 15 | ns | See Figure 2.9 , CL = 15pF | 6 |
| Propagation Delay | tPHL | 5 | 10.56 | 15 | ns | See Figure 2.9 , CL = 15pF | 6 |
| Pulse Width Distortion | PWD |  |  | 5 | ns | See Figure 2.9 , CL = 15pF | 6 |
| Rising Time | tr |  |  | 5 | ns | See Figure 2.9 , CL = 15pF | 6 |
| Falling Time | tf |  |  | 5 | ns | See Figure 2.9 , CL = 15pF | 6 |
| Peak Eye Diagram Jitter | tJIT(PK) |  |  | 350 | ps |  | 6 |
| Channel-to-Channel Delay Skew | tSK(c2c) |  |  | 2.5 | ns |  | 6 |
| Part-to-Part Delay Skew | tSK(p2p) |  |  | 5 | ns |  | 6 |
| Data Rate | DR | 0 |  | 150 | Mbps |  | 6 |
| Power on Reset | VDDPOR |  | 2.2 |  | V | POR threshold as during power-up | 4 |
| POR threshold Hysteresis | VDD HYS |  | 0.1 |  | V | POR threshold Hysteresis | 4 |
| Input Threshold | VIT |  | 1.6 |  | V | Input Threshold at rising edge | 4 |
| Input Threshold Hysteresis | VIT_HYS |  | 0.4 |  | V | Input Threshold Hysteresis | 4 |
| Output Impedance | Rout |  | 50 |  | ohm |  | 4 |
| Start Up Time after POR | trbs |  | 40 |  | usec |  | 4 |
| IC Junction-to-Air Thermal Resistance | θJA |  | 78.9 |  | °C/W | NB-SOIC-16 column | 4 |
| Junction-to-case (top) thermal resistance | θJC（top） |  | 41.1 |  | °C/W | NB-SOIC-16 column | 4 |
| Junction-to-board thermal resistance | θJB |  | 49.5 |  | °C/W | NB-SOIC-16 column | 4 |
| Disable high to Tri-State | tPHZ |  | 14.88 |  | ns | See Figure 2.10 , CL = 15pF, RL=1k | 6 |
| Enable to Data high Valid | tPZH |  | 10 |  | ns | See Figure 2.10 , CL = 15pF, RL=1k | 6 |
| Disable low to Tri-State | tPLZ |  | 17.25 |  | ns | See Figure 2.10 , CL = 15pF, RL=1k | 6 |
| Enable to Data high Valid | tPZL |  | 10.85 |  | ns | See Figure 2.10 , CL = 15pF, RL=1k | 6 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC |  | In accordance with DIN VDE V 0884-11, each NSi8140N/NSi8141N/NSi8142N is proof tested by applying an insulation test voltage ≥ 847 V peak for 1 sec (partial discharge detection limit = 5 pC). The * ma | 14 |

## CAD (KiCad official)

- Symbol: `NSI8140N1`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `nsi8140n1-etched.step` / `nsi8140n1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nsi8140n1.step` / `nsi8140n1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [NOVOSENSE datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588947490787758080) (24 pp, sha256 `2b3812b6e5a434fb`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/nsi8140n1-datasheet.pdf)