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NSI8121N1

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NOVOSENSE Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NSI8121N1

NOVOSENSE · Digital Isolators · SOIC-8

NSI8121N1 from NOVOSENSE, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1, operating from 2.5 V to 5.5 V per the electrical characteristics, with absolute maximum rating of -0.5 V to 6.5 V.
2 OUTA output Logic output A on isolator side 1 side of the channel; output source/sink current is limited to 15 mA absolute maximum, with typical output impedance of about 50 Ω ±40%.
3 INB input Logic input B; input voltage must stay between -0.4 V and VDD+0.4 V (absolute maximum), with VIH of 2 V minimum and VIL of 0.8 V maximum.
4 GND1 power_in Ground 1, the ground reference for isolator side 1.
5 GND2 power_in Ground 2, the ground reference for isolator side 2.
6 OUTB output Logic output B; output current is limited to 15 mA absolute maximum, with typical output impedance of about 50 Ω ±40%.
7 INA input Logic input A; input voltage must stay between -0.4 V and VDD+0.4 V (absolute maximum), with VIH of 2 V minimum and VIL of 0.8 V maximum.
8 VDD2 power_in Power supply for isolator side 2, operating from 2.5 V to 5.5 V per the electrical characteristics, with absolute maximum rating of -0.5 V to 6.5 V.

Key specifications

Parameter Value
Manufacturer NOVOSENSE
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power Supply Voltage VDD1, VDD2 -0.5 6.5 V 3
Common-Mode Transients CMTI -150 150 kV/us 3
Output current Io -15 15 mA 3
Operating Temperature Topr -40 125 ℃ 3
Storage Temperature Tstg -40 150 ℃ 3
Electrostatic discharge HBM HBM -6000 6000 V 3
Electrostatic discharge CDM CDM -2000 2000 V 3
Power supply voltage (operating range) VDD1, VDD2 2.5 5.5 V Ta=-40℃ to 125℃ 3
Data Rate DR 0 150 Mbps 4
Common Mode Transient Immunity CMTI 100 150 kV/us 3
Power on Reset threshold VDDPOR 2.2 V POR threshold as during power-up 3
POR threshold hysteresis VDD HYS 0.1 V POR threshold Hysteresis 3
Input Threshold VIT 1.6 V Input Threshold at rising edge 3
Input Threshold Hysteresis VIT_HYS 0.4 V Input Threshold Hysteresis 3
High Level Input Voltage VIH 2 V 3
Low Level Input Voltage VIL 0.8 V 3
Low Level Output Voltage VOL 0.2 V IOL ≤ 4mA 3
Output Impedance Rout 50 ohm 3
Start Up Time after POR trbs 3 usec 3
Minimum Pulse Width PW 5 ns 4
Pulse Width Distortion PWD 5 ns /tPHL, tPLH/ 4
Rising Time tr 5 ns CL = 15pF 4
Falling Time tf 5 ns CL = 15pF 4
Peak Eye Diagram Jitter tJIT(PK) 350 ps 4
Channel-to-Channel Delay Skew tSK(c2c) 2.5 ns 5
Part-to-Part Delay Skew tSK(p2p) 5 ns 5
Propagation Delay (rising) tPLH 9 ns VDD1=VDD2=5V±10% 4
Propagation Delay (falling) tPHL 9 ns VDD1=VDD2=5V±10% 4
Propagation Delay (rising) tPLH 10 ns VDD1=VDD2=2.5V±10% 7
Propagation Delay (falling) tPHL 10 ns VDD1=VDD2=2.5V±10% 7
Supply current NSi8121/NSi8122 IDD1(Q0) 1.03 mA VDD1=5V±10%, VDD2=5V±10%; All Input 0V 4
Supply current NSi8121/NSi8122 IDD2(Q0) 1 mA VDD1=5V±10%, VDD2=5V±10%; All Input 0V 4
Supply current NSi8121/NSi8122 IDD1(Q1) 2.2 mA VDD1=5V±10%, VDD2=5V±10%; All Input at supply 4
Supply current NSi8121/NSi8122 IDD2(Q1) 2.13 mA VDD1=5V±10%, VDD2=5V±10%; All Input at supply 4
Supply current NSi8121/NSi8122 IDD1(1M) 1.72 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 1Mbps, CL=15pF 4
Supply current NSi8121/NSi8122 IDD2(1M) 1.68 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 1Mbps, CL=15pF 4
Supply current NSi8121/NSi8122 IDD1(10M) 2.62 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 10Mbps, CL=15pF 4
Supply current NSi8121/NSi8122 IDD2(10M) 2.71 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 10Mbps, CL=15pF 4
Supply current NSi8121/NSi8122 IDD1(100M) 11.01 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 100Mbps, CL = 15pF 4
Supply current NSi8121/NSi8122 IDD2(100M) 12.8 mA VDD1=5V±10%, VDD2=5V±10%; All Input with 100Mbps, CL = 15pF 4
Supply current NSi8121/NSi8122 IDD1(Q0) 0.98 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input 0V 5
Supply current NSi8121/NSi8122 IDD2(Q0) 0.95 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input 0V 5
Supply current NSi8121/NSi8122 IDD1(Q1) 2.14 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input at supply 5
Supply current NSi8121/NSi8122 IDD2(Q1) 2.08 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input at supply 5
Supply current NSi8121/NSi8122 IDD1(1M) 1.63 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 1Mbps, CL = 15pF 5
Supply current NSi8121/NSi8122 IDD2(1M) 1.59 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 1Mbps, CL = 15pF 5
Supply current NSi8121/NSi8122 IDD1(10M) 2.22 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 10Mbps, CL = 15pF 5
Supply current NSi8121/NSi8122 IDD2(10M) 2.25 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 10Mbps, CL = 15pF 5
Supply current NSi8121/NSi8122 IDD1(100M) 7.57 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 100Mbps, CL = 15pF 5
Supply current NSi8121/NSi8122 IDD2(100M) 8.5 mA VDD1=3.3V±10%, VDD2=3.3V±10%; All Input with 100Mbps, CL = 15pF 5
Supply current NSi8121/NSi8122 IDD1(Q0) 0.96 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input 0V 6
Supply current NSi8121/NSi8122 IDD2(Q0) 0.93 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input 0V 6
Supply current NSi8121/NSi8122 IDD1(Q1) 2.11 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input at supply 6
Supply current NSi8121/NSi8122 IDD2(Q1) 2.05 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input at supply 6
Supply current NSi8121/NSi8122 IDD1(1M) 1.58 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 1Mbps, CL = 15pF 6
Supply current NSi8121/NSi8122 IDD2(1M) 1.54 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 1Mbps, CL = 15pF 6
Supply current NSi8121/NSi8122 IDD1(10M) 2.02 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 10Mbps, CL = 15pF 6
Supply current NSi8121/NSi8122 IDD2(10M) 2.04 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 10Mbps, CL = 15pF 6
Supply current NSi8121/NSi8122 IDD1(100M) 6.03 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 100Mbps, CL = 15pF 6
Supply current NSi8121/NSi8122 IDD2(100M) 6 mA VDD1=2.5V±10%, VDD2=2.5V±10%; All Input with 100Mbps, CL = 15pF 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC In accordance with DIN V VDE V 0884-10, each NSi8120N/NSi8121N/NSi8122N is proof tested by applying an insulation test voltage ≥ 1059 V peak for 1 sec (partial discharge detection limit = 5 pC). The * 11

CAD (KiCad official)

  • Symbol: NSI8121N1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: nsi8121n1-etched.step / nsi8121n1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsi8121n1.step / nsi8121n1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NOVOSENSE datasheet (17 pp, sha256 433b8ba27019be02, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF