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NSI8120N1

Public Made by Adom

by adom

NOVOSENSE Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NSI8120N1

NOVOSENSE · Digital Isolators · SOIC-8

NSI8120N1 from NOVOSENSE, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Power supply for isolator side 1, operating from 2.5 V to 5.5 V with an absolute maximum of 6.5 V, and requires a 0.1 µF bypass capacitor to GND1.
2 INA input Logic input A on side 1, with VIH of 2 V minimum and VIL of 0.8 V maximum, and an absolute input voltage range of -0.4 V to VDD+0.4 V.
3 INB input Logic input B on side 1, with VIH of 2 V minimum and VIL of 0.8 V maximum, and an absolute input voltage range of -0.4 V to VDD+0.4 V.
4 GND1 power_in Ground 1, the ground reference for isolator side 1.
5 GND2 power_in Ground 2, the ground reference for isolator side 2.
6 OUTB output Logic output B on side 2, with a typical output impedance of about 50 Ω (±40%) and an absolute output current rating of ±15 mA.
7 OUTA output Logic output A on side 2, with a typical output impedance of about 50 Ω (±40%) and an absolute output current rating of ±15 mA.
8 VDD2 power_in Power supply for isolator side 2, operating from 2.5 V to 5.5 V with an absolute maximum of 6.5 V, and requires a 0.1 µF bypass capacitor to GND2.

Key specifications

Parameter Value
Manufacturer NOVOSENSE
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Pull high or low Current Ipull 8 15 uA 4
Common-Mode Transient Immunity CMTI -100 150 kV/us 4
Start Up Time after POR trbs 40 usec 4
Low Level Input Voltage VIL 0.8 V 3
High Level Input Voltage VIH 2 V 3
Low Level Output Voltage VOL 0.3 V IOL ≤ 4mA 3
Data Rate DR 0 150 Mbps 4
Minimum Pulse Width PW 5 ns 4
Pulse Width Distortion /tPHL, tPLH/ PWD 5 ns See Figure 2.7, CL = 15pF 5
Rising Time tr 5 ns See Figure 2.7, CL = 15pF 5
Falling Time tf 5 ns See Figure 2.7, CL = 15pF 5
Peak Eye Diagram Jitter tJIT(PK) 350 ps 5
Channel-to-Channel Delay Skew tSK(c2c) 2.5 ns 5
Part-to-Part Delay Skew tSK(p2p) 5 ns 5
Propagation Delay (rising) tPLH 5 8.2 15 ns VDD=5V±10%; See Figure 2.7, CL = 15pF 5
Propagation Delay (falling) tPHL 5 10.56 15 ns VDD=5V±10%; See Figure 2.7, CL = 15pF 5
Propagation Delay (rising) tPLH 5 10 15 ns VDD=2.5V±10%; See Figure 2.7, CL = 15pF 7
Propagation Delay (falling) tPHL 5 10 15 ns VDD=2.5V±10%; See Figure 2.7, CL = 15pF 7
Supply current VDD1 (NSi8120) IDD1(Q0) 0.58 0.87 mA VDD=5V±10%; All Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 4
Supply current VDD2 (NSi8120) IDD2(Q0) 1.18 1.77 mA VDD=5V±10%; All Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 4
Supply current VDD1 (NSi8120) IDD1(Q1) 2.92 4.38 mA VDD=5V±10%; All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1 4
Supply current VDD2 (NSi8120) IDD2(Q1) 1.24 1.86 mA VDD=5V±10%; All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1 4
Supply current VDD1 (NSi8120) IDD1(1M) 1.71 2.56 mA VDD=5V±10%; All Input with 1Mbps, CL=15pF 4
Supply current VDD2 (NSi8120) IDD2(1M) 1.38 2.07 mA VDD=5V±10%; All Input with 1Mbps, CL=15pF 4
Supply current VDD1 (NSi8120) IDD1(10M) 1.78 2.67 mA VDD=5V±10%; All Input with 10Mbps, CL=15pF 4
Supply current VDD2 (NSi8120) IDD2(10M) 3.2 4.8 mA VDD=5V±10%; All Input with 10Mbps, CL=15pF 4
Supply current VDD1 (NSi8120) IDD1(100M) 2.1 3.15 mA VDD=5V±10%; All Input with 100Mbps, CL=15pF 4
Supply current VDD2 (NSi8120) IDD2(100M) 21 31.5 mA VDD=5V±10%; All Input with 100Mbps, CL=15pF 4
Supply current VDD1 (NSi8120) IDD1(Q0) 0.53 0.8 mA VDD=2.5V±10%; All Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 6
Supply current VDD2 (NSi8120) IDD2(Q0) 1.1 1.65 mA VDD=2.5V±10%; All Input 0V for NSi8120x0 Or All Input at supply for NSi8120x1 6
Supply current VDD1 (NSi8120) IDD1(Q1) 2.85 4.28 mA VDD=2.5V±10%; All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1 6
Supply current VDD2 (NSi8120) IDD2(Q1) 1.15 1.73 mA VDD=2.5V±10%; All Input at supply for NSi8120x0 Or All Input 0V for NSi8120x1 6
Supply current VDD1 (NSi8120) IDD1(1M) 1.63 2.45 mA VDD=2.5V±10%; All Input with 1Mbps, CL = 15pF 6
Supply current VDD2 (NSi8120) IDD2(1M) 1.21 1.82 mA VDD=2.5V±10%; All Input with 1Mbps, CL = 15pF 6
Supply current VDD1 (NSi8120) IDD1(10M) 1.68 2.52 mA VDD=2.5V±10%; All Input with 10Mbps, CL = 15pF 6
Supply current VDD2 (NSi8120) IDD2(10M) 2.05 3.08 mA VDD=2.5V±10%; All Input with 10Mbps, CL = 15pF 6
Supply current VDD1 (NSi8120) IDD1(100M) 1.95 2.93 mA VDD=2.5V±10%; All Input with 100Mbps, CL = 15pF 6
Supply current VDD2 (NSi8120) IDD2(100M) 10.4 15.6 mA VDD=2.5V±10%; All Input with 100Mbps, CL = 15pF 6
Power Supply Voltage VDD1, VDD2 -0.5 6.5 V 3
Maximum Input Voltage VINA, VINB -0.4 V 3
Maximum Output Voltage VOUTA, VOUTB -0.4 V 3
Maximum Input/Output Pulse Voltage VINA, VINB, VOUTA, VOUTB -0.8 V Pulse width less than 100ns, duty cycle less than 10% 3
Output current Io -15 15 mA 3
Maximum Surge Isolation Voltage VIOSM 5.3 kV 3
Operating Temperature Topr -40 125 ℃ 3
Storage Temperature Tstg -40 150 ℃ 3
Electrostatic discharge HBM HBM -6000 6000 V 3
Electrostatic discharge CDM CDM -2000 2000 V 3
Common-Mode Transients CMTI -150 150 kV/us 3
Supply voltage VDD1 VDD1 2.5 5.5 V 3
Supply voltage VDD2 VDD2 2.5 5.5 V 3
Power on Reset threshold VDDPOR 2.2 V POR threshold as during power-up 3
POR threshold Hysteresis VDD HYS 0.1 V POR threshold Hysteresis 3
Input Threshold VIT 1.6 V Input Threshold at rising edge 3
Input Threshold Hysteresis VIT_HYS 0.4 V Input Threshold Hysteresis 3
Output Impedance Rout 50 ohm 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing pC 2 In accordance with DIN VDE V 0884-11, each NSi8120N/NSi8121N/NSi8122N is proof tested by applying an insulation test voltage ≥ 847 V peak for 1 sec (partial discharge detection limit = 5 pC). The * 11

CAD (KiCad official)

  • Symbol: NSI8120N1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: nsi8120n1-etched.step / nsi8120n1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsi8120n1.step / nsi8120n1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NOVOSENSE datasheet (21 pp, sha256 ecafd88bc81f54ad, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF