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NS4871

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Shenzhen Nsiway Tech Audio Amplifiers, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs Publish 0.1.0 · Ray 19d ago
viewers ns4871: viewers · Ray 19d ago
ns4871-etched.glb ns4871: factory component page (tier=lcsc) · Ray 19d ago
ns4871-etched.step ns4871: factory component page (tier=lcsc) · Ray 19d ago
ns4871-hero.glb ns4871: hero GLB from the etched model (keeps the MPN mark) · Ray 19d ago
ns4871-hero.overlay.json Publish 0.1.0 · Ray 19d ago
ns4871.glb Publish 0.1.0 · Ray 19d ago
ns4871.kicad_mod Publish 0.1.0 · Ray 19d ago
ns4871.kicad_sym Publish 0.1.0 · Ray 19d ago
ns4871.lbr Publish 0.1.0 · Ray 19d ago
ns4871.step Publish 0.1.0 · Ray 19d ago
package.json Publish 0.1.0 · Ray 19d ago
page.json ns4871: specified limits as data (metadata.characteristics, 25 rows from the datasheet) · Ray 13d ago
README.md ns4871: specified limits as data (metadata.characteristics, 25 rows from the datasheet) · Ray 13d ago

NS4871

Shenzhen Nsiway Tech · Audio Amplifiers · SOP-8-EP

NS4871 from Shenzhen Nsiway Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD input Shutdown control pin: a high level puts the amplifier into shutdown and a low level enables it, and the control level must meet the interface requirements (VIH 1.5 V / VIL 1.3 V at 5 V supply; VIH 1.3 V / VIL 1.0 V at 3 V supply).
2 Bypass passive Internal common-mode voltage bypass pin, where an external capacitor CB (typically 0.1 uF to 1 uF ceramic) affects PSRR and switching noise.
3 +IN input Non-inverting analog input of the amplifier, with gain set by the external resistors Ri and Rf (Av = 2 x Rf / Ri).
4 -IN input Inverting analog input of the amplifier, with gain set by the external resistors Ri and Rf (Av = 2 x Rf / Ri).
5 VO1 output Analog output 1 of the BTL bridge output, driving one side of the load.
6 VDD power_in Positive power supply, specified at 3.0 V to 5.25 V with input voltage limited to -0.3 V to VDD.
7 GND power_in Power supply ground.
8 VO2 output Analog output 2 of the BTL bridge output, driving the other side of the load in inverted phase to VO1.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Shenzhen Nsiway Tech
Package SOP-8-EP
Category Amplifiers/Comparators
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage range (limiting parameters) 2.8 5.5 V 2
Power supply voltage VDD 3 5.25 V 4
Input voltage range (max is VDD) -0.3 V 2
ESD voltage, human body model 3000 V HBM 2
ESD voltage, machine model 250 V MM 2
Operating temperature range -40 85 ℃ 2
Storage temperature range -65 150 ℃ 2
Maximum junction temperature 150 ℃ 2
Soldering temperature 220 ℃ 10 s 2
Quiescent supply current IDD 6 10 mA VIN=0V, Io=0A 4
Shutdown leakage current ISD 1 20 µA 4
Output offset voltage VOS 5.7 50 mV 4
Output resistance RO 7 8.5 10 K 4
Power supply rejection ratio PSRR 65 80 dB 4
Output power PO 2 W THD=1%, f=1kHz, RL=4Ω 4
Output power PO 1.3 W THD=1%, f=1kHz, RL=8Ω 4
Output power PO 1.7 W THD+N=10%, f=1kHz, RL=8Ω 4
Total harmonic distortion plus noise THD+N 0.1 % AVD=2, 20Hz≤f≤20kHz, RL=4Ω, PO=1W 4
Signal-to-noise ratio SNR 85 dB RL=4Ω, Po=1W 4
Shutdown input high-level voltage (VDD = 5V) VIH 1.5 V VDD=5V 12
Shutdown input low-level voltage (VDD = 5V) VIL 1.3 V VDD=5V 12
Shutdown input high-level voltage (VDD = 3V) VIH 1.3 V VDD=3V 12
Shutdown input low-level voltage (VDD = 3V) VIL 1 V VDD=3V 12
Thermal resistance, junction-to-case θJC 35 °C/W 2
Thermal resistance, junction-to-ambient θJA 140 °C/W 2

CAD (KiCad official)

  • Symbol: NS4871
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: ns4871-etched.step / ns4871-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ns4871.step / ns4871.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Shenzhen Nsiway Tech datasheet (14 pp, sha256 1a911e8bc37ac0fc, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF