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ns4263

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Shenzhen Nsiway Tech Audio Power OpAmps, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ns4263: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers ns4263: viewers · Ray 2mo ago
ns4263-etched.fit.json ns4263: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ns4263-etched.glb ns4263: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ns4263-etched.step ns4263: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ns4263.glb Publish 0.1.0 · Ray 2mo ago
ns4263.kicad_mod Publish 0.1.0 · Ray 2mo ago
ns4263.kicad_sym Publish 0.1.0 · Ray 2mo ago
ns4263.lbr Publish 0.1.0 · Ray 2mo ago
ns4263.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.1.0 · Ray 2mo ago
page.json ns4263: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 28d ago
README.md ns4263: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

NS4263

Shenzhen Nsiway Tech · Audio Power OpAmps · SOIC-16

NS4263 from Shenzhen Nsiway Tech, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SD input Shutdown and Class-AB/Class-D mode-select control via one-wire pulse (VIH=1.4V min, VIL=0.4V max). A logic high held >100 us places the chip in low-power shutdown; a single falling edge sets Class-AB, two consecutive falling edges set Class-D. THI/TLO pulse widths must be 1-12 us.
2 GND power_in Device ground / power return. Connect together with pins 7 and 15 to the board ground plane.
3 VoPA output Left-channel BTL positive output. Drives one side of the left speaker (4-8 Ω typical) in bridge-tied load mode; in single-ended headphone mode this side is coupled through the 100 uF output cap.
4 VDD power_in Main analog/PWM supply input, 3.0-5.5 V operating (6 V abs max). Bypass with 10 uF electrolytic in parallel with 0.1 uF ceramic close to the pin; tie together with pin 13.
5 VoNA output Left-channel BTL negative output. Drives the return side of the left speaker in bridge mode; used as the left-channel single-ended output to the headphone jack via the 100 uF DC-blocking capacitor.
6 INNA input Left-channel inverting audio input. AC-coupled through Ci (0.1-0.39 uF) and series input resistor Ri (typ. 20 kΩ); gain per channel Av = 240k / Rin. Non-inverting input is tied internally to VREF.
7 GND power_in Device ground / power return. Tie together with pins 2 and 15 to the ground plane.
8 NC unconnected No internal connection. Leave floating or tie to ground per PCB convenience.
9 NC unconnected No internal connection. Leave floating or tie to ground per PCB convenience.
10 VREF passive Internal mid-supply bias reference (approx. VDD/2). Requires a 1 uF bypass capacitor Cb to GND; the cap value sets startup ramp / pop-noise behavior.
11 INNB input Right-channel inverting audio input. AC-coupled through Ci (0.1-0.39 uF) and series input resistor Ri (typ. 20 kΩ); gain per channel Av = 240k / Rin. Non-inverting input is tied internally to VREF.
12 VoNB output Right-channel BTL negative output. Drives the return side of the right speaker in bridge mode; used as the right-channel single-ended output to the headphone jack via the 100 uF DC-blocking capacitor.
13 VDD power_in Main analog/PWM supply input, 3.0-5.5 V operating (6 V abs max). Tie together with pin 4 and bypass with 10 uF electrolytic in parallel with 0.1 uF ceramic close to the pin.
14 VoPB output Right-channel BTL positive output. Drives one side of the right speaker (4-8 Ω typical) in bridge-tied load mode.
15 GND power_in Device ground / power return. Tie together with pins 2 and 7 to the ground plane.
16 HP-IN input Headphone-mode select input (VIH=1.4V min, VIL=0.4V max). Logic low = BTL speaker mode; logic high = single-ended stereo headphone mode. Typically driven from a resistor divider off the headphone jack's mechanical switch (HP CONTROL) so plug insertion auto-switches the output topology.

Key specifications

Parameter Value
Manufacturer Shenzhen Nsiway Tech
Package SOIC-16
Category Op-amp/Cmp
Pins 16

CAD (KiCad official)

  • Symbol: NS4263
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ns4263-etched.step / ns4263-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ns4263.step / ns4263.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Shenzhen Nsiway Tech datasheet (None pp, sha256 7be7db0e3e023b07, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF