NPCA110PA0YX

Nuvoton Tech · Audio Power OpAmps · QFN-40-EP(6x6)

NPCA110PA0YX from Nuvoton Tech, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GPIO02/SDI0	bidirectional	General-purpose I/O signal 02 or I2S serial data input 0 carrying input stereo data stream 0, with internal pull-up, 5V tolerant, O2/2 buffer.
2	GPIO03/SDI1	bidirectional	General-purpose I/O signal 03 or I2S serial data input 1 carrying input stereo data stream 1, with internal pull-up, 5V tolerant, O2/2 buffer.
3	GPIO04	bidirectional	General-purpose I/O signal 04 with internal pull-up, 5V tolerant, O2/2 buffer.
4	VDD	power_in	3.3V digital supply, decoupled with 0.1 uF to ground near each VDD pin and a 10 uF or larger bulk capacitor.
5	RIN1	input	Analog right input of ADC input pair 1 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected).
6	LIN1	input	Analog left input of ADC input pair 1 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected).
7	RIN3	input	Analog right input of ADC input pair 3 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected).
8	RIN2	input	Analog right input of ADC input pair 2 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected).
9	LIN2	input	Analog left input of ADC input pair 2 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected).
10	LOUT2	output	Analog left output 2 of DAC2, used as the bass channel output in 2.1 output configurations.
11	ROUT2	output	Analog right output 2 of DAC2.
12	LIN3	input	Analog left input of ADC input pair 3 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected).
13	DAC_REF	passive	Internally generated DAC reference voltage, connected via a 0.1 uF ceramic capacitor in parallel with a 22 uF tantalum/ceramic capacitor to AVSS.
14	VCM	passive	Internally generated CODEC common-mode voltage, connected via a 0.1 uF ceramic capacitor in parallel with a 22 uF tantalum/ceramic capacitor to AVSS.
15	AGND	power_in	CODEC analog ground return, connected to the analog ground plane, which joins the digital ground plane at one point near the device.
16	ADC_REF	passive	Internally generated ADC reference voltage, connected via a 0.1 uF ceramic capacitor in parallel with a 22 uF tantalum/ceramic capacitor to AVSS.
17	AVDD	power_in	CODEC analog 3.3V supply (3.00V to 3.47V) from a filtered supply, bypassed with 0.1 uF ceramic and 22 uF capacitors to AVSS.
18	LOUT1	output	Analog left output 1 of the DAC, the main left output.
19	ROUT1	output	Analog right output 1 of the DAC, the main right output.
20	VDD	power_in	3.3V digital supply (3.13V to 3.47V) for the I/O interface and internal regulators.
21	XTALI/CLKIN	input	Crystal clock input (12.288 MHz for 48 KHz or 11.2896 MHz for 44.1 KHz sample rate) or LVTTL clock input.
22	XTALO	output	Crystal clock output used for the crystal connection circuit.
23	VPLL18	power_out	Internally generated 1.8V PLL supply, connected via a 4.7 uF ceramic capacitor to VSSP.
24	VSSP	power_in	PLL ground, connected to the digital ground plane via a 0 ohm resistor.
25	GPIO20	bidirectional	General-purpose I/O signal 20 with internal pull-up, 5V tolerant, O2/2 buffer.
26	VD18	power_out	Internally generated 1.8V supply for internal logic, connected via a 4.7 uF ceramic capacitor to digital ground.
27	VDD	power_in	3.3V digital supply, decoupled with 0.1 uF to ground near each VDD pin.
28	nRESET	input	Power-up reset input that forces reset when driven low, with internal pull-up, 5V tolerant Schmitt trigger.
29	GPO18/SDO2/I2CMS	output	General-purpose output 18 or I2S serial data out 2 (33 to 100 ohm series resistor required), and I2C master/slave strap sampled at power-up reset (pulled up selects slave, 8.2 K pull-down selects master).
30	SDA	bidirectional	Master/slave I2C data line, Schmitt trigger input, 5V tolerant, OD6 open-drain buffer.
31	N.C.	unconnected	Not connected; must be left open and not connected to any signal.
32	SCL	bidirectional	Master/slave I2C clock line, Schmitt trigger input that ignores pulses shorter than 5 ns, 5V tolerant, OD6 open-drain buffer.
33	GPIO15	bidirectional	General-purpose I/O signal 15 with internal pull-up, 5V tolerant, O2/2 buffer.
34	GPIO19	bidirectional	General-purpose I/O signal 19 with internal pull-up, 5V tolerant, O2/2 buffer.
35	GPO17	output	General-purpose output signal 17 with internal pull-up, 5V tolerant, O8/8 buffer.
36	GPIO00/DCLK	bidirectional	General-purpose I/O signal 00 or I2S clock (input for slave, output for master) at 32 or 64 times the sample frequency, with a 33 to 100 ohm series resistor when used as output.
37	VDD	power_in	3.3V digital supply, decoupled with 0.1 uF to ground near each VDD pin.
38	GPIO01/SYNC	bidirectional	General-purpose I/O signal 01 or I2S SYNC (input for slave, output for master) indicating the sample frequency, with a 33 to 100 ohm series resistor when used as output.
39	GPO06/SDO0/nTEST	output	General-purpose output 06 or I2S serial data out 0 (33 to 100 ohm series resistor required), and test strap sampled during power-up reset (internal pull-up for normal operation, 8.2 K pull-down sets 0).
40	GPO07/SDO1/CLKOUT/REF	output	General-purpose output 07, I2S serial data out 1 or general-purpose clock output (33 to 100 ohm series resistor required), and reference strap sampled at power-up (pull-up selects DCLK in, 8.2 K pull-down selects crystal oscillator).
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	QFN-40-EP(6x6)
Category	Amplifiers
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
3.3V Supply Voltage (VDD pins)	VDD	3.13	3.3	3.47	V		18
3.3V Analog Supply Voltage (AVDD pin)	AVDD	3	3.3	3.47	V		18
VDD and AVDD Power Off Voltage	VOFF	0.3	0	0.5	V		18
Operating Ambient Temperature	TA	0		70	C		18
VDD 3.3V Supply Voltage, including AVDD	VDD	0.5		3.6	V		18
Input Voltage, all buffer types (except analog)	VI	0.5			V	All buffer types (except analog)	18
Input Voltage, 5V buffer types	VI	0.5		5.5	V	5V buffer types	18
Input Voltage, all digital signals when VDD < 0.5V	VI	0.5		3.47	V	VDD < 0.5V, all digital signals	18
Output Voltage, all buffer types (except analog)	VO	0.5			V	All buffer types (except analog)	18
Total NPCA110P Sink or Source Current	ISINK			50	mA	Total of all output pins	18
ESD Tolerance				2000	V	CZAP = 100 pF, RZAP = 1.5 K	18
Storage Temperature	TSTG	65		150	C		18
Ambient Temperature Under Bias	TBIAS	0		70	C		18
Power Dissipation	PD			0.5	W	For correct operation	18
I/O Pin Capacitance	CIO		8	12	pF	All pins; TA = 25C, f = 1 MHz	18
VDD Average Supply Current (including ADC, DACs)	IDD		55	704	mA	Active; VIL = 0.5V, VIH = 2.4V, DAC load = 10 K; processor clock 125 MHz	19
VDD Stop Supply Current	IDD			0.7	mA	Idle	19
ADC Average Current	IADC			46	mA	Active	19
Each DAC Average Current	IDAC		2.5	5	mA	Active; RL = 10 K	19
Input High Voltage, non-5V types (TTL input)	VIH	2			V	Non-5V types	19
Input High Voltage, 5V types (TTL input)	VIH	2		5.5	V	5V types	19
Input Low Voltage (TTL input)	VIL	0.5		0.8	V		19
Input Leakage Current (TTL input)	IILK			2	uA	VDD = 3.13V-3.47V and 0 < VIN < VDD	19
Input High Voltage, non-5V types (Schmitt trigger input)	VIH	2			V	Non-5V types	19
Input High Voltage, 5V types (Schmitt trigger input)	VIH	2		5.5	V	5V types	19
Input Low Voltage (Schmitt trigger input)	VIL	0.5		0.8	V		19
Input Leakage Current (Schmitt trigger input)	IILK			2	uA	VDD = 3.13V-3.47V and 0 < VIN < VDD	19
Output High Voltage	VOH	2.4			V	IOH = p mA	20
Output Low Voltage	VOL			0.4	V	IOL = n mA	20
Output Low Voltage	VOL			0.2	V	IOL = 50 uA	20
Output Leakage Current (push-pull)	IOLK			2	uA	VDD = 3.13V-3.47V and 0 < VIN < VDD	20
Output Low Voltage (open-drain)	VOL			0.4	V	IOL = n mA	20
Output Low Voltage (open-drain)	VOL			0.2	V	IOL = 50 uA	20
Output Leakage Current (open-drain)	IOLK			2	uA	VDD = 3.13V-3.47V and 0 < VIN < VDD	20
Pull-Up Equivalent Resistance for other pins	RPU	34	60	95	K	VPIN = 0V; TA = 0C to 70C, VSUP = 3.3V ±5%	21
nRESET Pulse Width	tPRST	1			ms	To assure reset	24
Theta JA, 40-Pin QFN, 0 m/s airflow	ThetaJA		57		degrees Kelvin/Watt	0 m/s; device soldered to 4-layer PCB	29
Theta JA, 40-Pin QFN, 1 m/s airflow	ThetaJA		49		degrees Kelvin/Watt	1 m/s; device soldered to 4-layer PCB	29
Theta JA, 40-Pin QFN, 2 m/s airflow	ThetaJA		47		degrees Kelvin/Watt	2 m/s; device soldered to 4-layer PCB	29

CAD (KiCad official)

Symbol: NPCA110PA0YX
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: npca110pa0yx-etched.step / npca110pa0yx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); npca110pa0yx.step / npca110pa0yx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (31 pp, sha256 790dae220485ab2c, retrieved 2026-10-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# NPCA110PA0YX

**Nuvoton Tech** · Audio Power OpAmps · QFN-40-EP(6x6)

NPCA110PA0YX from Nuvoton Tech, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GPIO02/SDI0 | bidirectional | General-purpose I/O signal 02 or I2S serial data input 0 carrying input stereo data stream 0, with internal pull-up, 5V tolerant, O2/2 buffer. |
| 2 | GPIO03/SDI1 | bidirectional | General-purpose I/O signal 03 or I2S serial data input 1 carrying input stereo data stream 1, with internal pull-up, 5V tolerant, O2/2 buffer. |
| 3 | GPIO04 | bidirectional | General-purpose I/O signal 04 with internal pull-up, 5V tolerant, O2/2 buffer. |
| 4 | VDD | power_in | 3.3V digital supply, decoupled with 0.1 uF to ground near each VDD pin and a 10 uF or larger bulk capacitor. |
| 5 | RIN1 | input | Analog right input of ADC input pair 1 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected). |
| 6 | LIN1 | input | Analog left input of ADC input pair 1 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected). |
| 7 | RIN3 | input | Analog right input of ADC input pair 3 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected). |
| 8 | RIN2 | input | Analog right input of ADC input pair 2 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected). |
| 9 | LIN2 | input | Analog left input of ADC input pair 2 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected). |
| 10 | LOUT2 | output | Analog left output 2 of DAC2, used as the bass channel output in 2.1 output configurations. |
| 11 | ROUT2 | output | Analog right output 2 of DAC2. |
| 12 | LIN3 | input | Analog left input of ADC input pair 3 requiring AC coupling with a 1 uF capacitor (0.33 uF if 30 K input impedance is selected). |
| 13 | DAC_REF | passive | Internally generated DAC reference voltage, connected via a 0.1 uF ceramic capacitor in parallel with a 22 uF tantalum/ceramic capacitor to AVSS. |
| 14 | VCM | passive | Internally generated CODEC common-mode voltage, connected via a 0.1 uF ceramic capacitor in parallel with a 22 uF tantalum/ceramic capacitor to AVSS. |
| 15 | AGND | power_in | CODEC analog ground return, connected to the analog ground plane, which joins the digital ground plane at one point near the device. |
| 16 | ADC_REF | passive | Internally generated ADC reference voltage, connected via a 0.1 uF ceramic capacitor in parallel with a 22 uF tantalum/ceramic capacitor to AVSS. |
| 17 | AVDD | power_in | CODEC analog 3.3V supply (3.00V to 3.47V) from a filtered supply, bypassed with 0.1 uF ceramic and 22 uF capacitors to AVSS. |
| 18 | LOUT1 | output | Analog left output 1 of the DAC, the main left output. |
| 19 | ROUT1 | output | Analog right output 1 of the DAC, the main right output. |
| 20 | VDD | power_in | 3.3V digital supply (3.13V to 3.47V) for the I/O interface and internal regulators. |
| 21 | XTALI/CLKIN | input | Crystal clock input (12.288 MHz for 48 KHz or 11.2896 MHz for 44.1 KHz sample rate) or LVTTL clock input. |
| 22 | XTALO | output | Crystal clock output used for the crystal connection circuit. |
| 23 | VPLL18 | power_out | Internally generated 1.8V PLL supply, connected via a 4.7 uF ceramic capacitor to VSSP. |
| 24 | VSSP | power_in | PLL ground, connected to the digital ground plane via a 0 ohm resistor. |
| 25 | GPIO20 | bidirectional | General-purpose I/O signal 20 with internal pull-up, 5V tolerant, O2/2 buffer. |
| 26 | VD18 | power_out | Internally generated 1.8V supply for internal logic, connected via a 4.7 uF ceramic capacitor to digital ground. |
| 27 | VDD | power_in | 3.3V digital supply, decoupled with 0.1 uF to ground near each VDD pin. |
| 28 | nRESET | input | Power-up reset input that forces reset when driven low, with internal pull-up, 5V tolerant Schmitt trigger. |
| 29 | GPO18/SDO2/I2CMS | output | General-purpose output 18 or I2S serial data out 2 (33 to 100 ohm series resistor required), and I2C master/slave strap sampled at power-up reset (pulled up selects slave, 8.2 K pull-down selects master). |
| 30 | SDA | bidirectional | Master/slave I2C data line, Schmitt trigger input, 5V tolerant, OD6 open-drain buffer. |
| 31 | N.C. | unconnected | Not connected; must be left open and not connected to any signal. |
| 32 | SCL | bidirectional | Master/slave I2C clock line, Schmitt trigger input that ignores pulses shorter than 5 ns, 5V tolerant, OD6 open-drain buffer. |
| 33 | GPIO15 | bidirectional | General-purpose I/O signal 15 with internal pull-up, 5V tolerant, O2/2 buffer. |
| 34 | GPIO19 | bidirectional | General-purpose I/O signal 19 with internal pull-up, 5V tolerant, O2/2 buffer. |
| 35 | GPO17 | output | General-purpose output signal 17 with internal pull-up, 5V tolerant, O8/8 buffer. |
| 36 | GPIO00/DCLK | bidirectional | General-purpose I/O signal 00 or I2S clock (input for slave, output for master) at 32 or 64 times the sample frequency, with a 33 to 100 ohm series resistor when used as output. |
| 37 | VDD | power_in | 3.3V digital supply, decoupled with 0.1 uF to ground near each VDD pin. |
| 38 | GPIO01/SYNC | bidirectional | General-purpose I/O signal 01 or I2S SYNC (input for slave, output for master) indicating the sample frequency, with a 33 to 100 ohm series resistor when used as output. |
| 39 | GPO06/SDO0/nTEST | output | General-purpose output 06 or I2S serial data out 0 (33 to 100 ohm series resistor required), and test strap sampled during power-up reset (internal pull-up for normal operation, 8.2 K pull-down sets 0). |
| 40 | GPO07/SDO1/CLKOUT/REF | output | General-purpose output 07, I2S serial data out 1 or general-purpose clock output (33 to 100 ohm series resistor required), and reference strap sampled at power-up (pull-up selects DCLK in, 8.2 K pull-down selects crystal oscillator). |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nuvoton Tech |
| Package | QFN-40-EP(6x6) |
| Category | Amplifiers |
| Pins | 41 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 3.3V Supply Voltage (VDD pins) | VDD | 3.13 | 3.3 | 3.47 | V |  | 18 |
| 3.3V Analog Supply Voltage (AVDD pin) | AVDD | 3 | 3.3 | 3.47 | V |  | 18 |
| VDD and AVDD Power Off Voltage | VOFF | 0.3 | 0 | 0.5 | V |  | 18 |
| Operating Ambient Temperature | TA | 0 |  | 70 | C |  | 18 |
| VDD 3.3V Supply Voltage, including AVDD | VDD | 0.5 |  | 3.6 | V |  | 18 |
| Input Voltage, all buffer types (except analog) | VI | 0.5 |  |  | V | All buffer types (except analog) | 18 |
| Input Voltage, 5V buffer types | VI | 0.5 |  | 5.5 | V | 5V buffer types | 18 |
| Input Voltage, all digital signals when VDD < 0.5V | VI | 0.5 |  | 3.47 | V | VDD < 0.5V, all digital signals | 18 |
| Output Voltage, all buffer types (except analog) | VO | 0.5 |  |  | V | All buffer types (except analog) | 18 |
| Total NPCA110P Sink or Source Current | ISINK |  |  | 50 | mA | Total of all output pins | 18 |
| ESD Tolerance |  |  |  | 2000 | V | CZAP = 100 pF, RZAP = 1.5 K | 18 |
| Storage Temperature | TSTG | 65 |  | 150 | C |  | 18 |
| Ambient Temperature Under Bias | TBIAS | 0 |  | 70 | C |  | 18 |
| Power Dissipation | PD |  |  | 0.5 | W | For correct operation | 18 |
| I/O Pin Capacitance | CIO |  | 8 | 12 | pF | All pins; TA = 25C, f = 1 MHz | 18 |
| VDD Average Supply Current (including ADC, DACs) | IDD |  | 55 | 704 | mA | Active; VIL = 0.5V, VIH = 2.4V, DAC load = 10 K; processor clock 125 MHz | 19 |
| VDD Stop Supply Current | IDD |  |  | 0.7 | mA | Idle | 19 |
| ADC Average Current | IADC |  |  | 46 | mA | Active | 19 |
| Each DAC Average Current | IDAC |  | 2.5 | 5 | mA | Active; RL = 10 K | 19 |
| Input High Voltage, non-5V types (TTL input) | VIH | 2 |  |  | V | Non-5V types | 19 |
| Input High Voltage, 5V types (TTL input) | VIH | 2 |  | 5.5 | V | 5V types | 19 |
| Input Low Voltage (TTL input) | VIL | 0.5 |  | 0.8 | V |  | 19 |
| Input Leakage Current (TTL input) | IILK |  |  | 2 | uA | VDD = 3.13V-3.47V and 0 < VIN < VDD | 19 |
| Input High Voltage, non-5V types (Schmitt trigger input) | VIH | 2 |  |  | V | Non-5V types | 19 |
| Input High Voltage, 5V types (Schmitt trigger input) | VIH | 2 |  | 5.5 | V | 5V types | 19 |
| Input Low Voltage (Schmitt trigger input) | VIL | 0.5 |  | 0.8 | V |  | 19 |
| Input Leakage Current (Schmitt trigger input) | IILK |  |  | 2 | uA | VDD = 3.13V-3.47V and 0 < VIN < VDD | 19 |
| Output High Voltage | VOH | 2.4 |  |  | V | IOH = p mA | 20 |
| Output Low Voltage | VOL |  |  | 0.4 | V | IOL = n mA | 20 |
| Output Low Voltage | VOL |  |  | 0.2 | V | IOL = 50 uA | 20 |
| Output Leakage Current (push-pull) | IOLK |  |  | 2 | uA | VDD = 3.13V-3.47V and 0 < VIN < VDD | 20 |
| Output Low Voltage (open-drain) | VOL |  |  | 0.4 | V | IOL = n mA | 20 |
| Output Low Voltage (open-drain) | VOL |  |  | 0.2 | V | IOL = 50 uA | 20 |
| Output Leakage Current (open-drain) | IOLK |  |  | 2 | uA | VDD = 3.13V-3.47V and 0 < VIN < VDD | 20 |
| Pull-Up Equivalent Resistance for other pins | RPU | 34 | 60 | 95 | K | VPIN = 0V; TA = 0C to 70C, VSUP = 3.3V ±5% | 21 |
| nRESET Pulse Width | tPRST | 1 |  |  | ms | To assure reset | 24 |
| Theta JA, 40-Pin QFN, 0 m/s airflow | ThetaJA |  | 57 |  | degrees Kelvin/Watt | 0 m/s; device soldered to 4-layer PCB | 29 |
| Theta JA, 40-Pin QFN, 1 m/s airflow | ThetaJA |  | 49 |  | degrees Kelvin/Watt | 1 m/s; device soldered to 4-layer PCB | 29 |
| Theta JA, 40-Pin QFN, 2 m/s airflow | ThetaJA |  | 47 |  | degrees Kelvin/Watt | 2 m/s; device soldered to 4-layer PCB | 29 |

## CAD (KiCad official)

- Symbol: `NPCA110PA0YX`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `npca110pa0yx-etched.step` / `npca110pa0yx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `npca110pa0yx.step` / `npca110pa0yx.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nuvoton Tech datasheet](docs/npca110pa0yx-datasheet.pdf) (31 pp, sha256 `790dae220485ab2c`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/npca110pa0yx-datasheet.pdf)