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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

NPCA110BA0YX

Nuvoton Tech · Audio Interface ICs · QFN-32-EP(5x5)

NPCA110BA0YX from Nuvoton Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	nRESET	input	Power-Up Reset Input that forces reset when driven low; 5V tolerant Schmitt trigger with internal pull-up resistor.
2	VDD	power_in	3.3V Digital Supply to I/O interface and internal regulators; supply range 3.13V to 3.47V.
3	VD18	power_in	Internal 1.8V Supply for internal logic; requires 4.7 µF ceramic capacitor to digital ground.
4	GPIO20/SDI0	input	I2S Serial Data In 0 carrying stereo input stream; 5V tolerant with internal pull-up and push-pull output capability for GPIO mode.
5	VSSP	power_in	PLL Ground; connect to digital ground plane via 0 Ω resistor.
6	VPLL18	power_in	PLL 1.8V Supply internally generated; requires 4.7 µF ceramic capacitor to VSSP.
7	XTALO	output	Crystal Clock Output used for crystal oscillator circuit connection.
8	XTALI/CLKIN	input	Crystal Clock Input or external clock input at LVTTL levels; supports 12.288 MHz (48 kHz) or 11.2896 MHz (44.1 kHz) crystals.
9	GPO18/I2CMS	output	General-Purpose Output Signal 18 that also functions as I2C Master/Slave strap sampled during power-up reset; 5V tolerant with internal pull-up.
10	VDD	power_in	3.3V Digital Supply to I/O interface and internal regulators; supply range 3.13V to 3.47V.
11	VSS	power_in	Digital Ground; connect to digital ground plane.
12	RIN1	input	Analog-to-Digital Converter Input Pair 1 Right Input; requires AC coupling with 1 µF (or 0.33 µF) capacitor.
13	LIN1	input	Analog-to-Digital Converter Input Pair 1 Left Input; requires AC coupling with 1 µF (or 0.33 µF) capacitor.
14	RIN2	input	Analog-to-Digital Converter Input Pair 2 Right Input; requires AC coupling with 1 µF (or 0.33 µF) capacitor.
15	LIN2	input	Analog-to-Digital Converter Input Pair 2 Left Input; requires AC coupling with 1 µF (or 0.33 µF) capacitor.
16	LOUT2	output	Digital-to-Analog Converter Left Output from DAC2.
17	ROUT2	output	Digital-to-Analog Converter Right Output from DAC2.
18	DAC_REF	power_out	CODEC Internally Generated DAC Reference Voltage; connect via 0.1 µF ceramic and 22 µF tantalum/ceramic capacitor to AVSS.
19	VCM	power_out	CODEC Internally Generated Common-Mode Voltage; connect via 0.1 µF ceramic and 22 µF tantalum/ceramic capacitor to AVSS.
20	AGND	power_in	CODEC Analog Ground; connect to analog ground plane and to digital ground at single point near AVDD pin.
21	AVDD	power_in	CODEC Analog 3.3V Supply (3.00V to 3.47V); requires 0.1 µF ceramic and 22 µF bypass capacitors to AVSS.
22	VSS	power_in	Digital Ground; connect to digital ground plane.
23	VDD	power_in	3.3V Digital Supply to I/O interface and internal regulators; supply range 3.13V to 3.47V.
24	GPO07/CLKOUT/REF	output	General-Purpose Clock Output that also functions as Reference strap sampled during power-up reset; 5V tolerant with pull-up; requires 33-100 Ω series resistor when used as output.
25	GPO06/SDO0/nTEST	output	I2S Serial Data Out 0 carrying stereo output stream that also functions as test strap sampled during power-up reset; 5V tolerant with pull-up; requires 33-100 Ω series resistor.
26	GPIO01/SYNC	bidirectional	I2S SYNC input for slave mode or output for master mode indicating sample frequency; 5V tolerant bidirectional with pull-up; requires 33-100 Ω series resistor when used as output.
27	VDD	power_in	3.3V Digital Supply to I/O interface and internal regulators; supply range 3.13V to 3.47V.
28	GPIO00/DCLK	bidirectional	I2S Clock input for slave mode or output for master mode (32x or 64x sample frequency); 5V tolerant bidirectional with pull-up; requires 33-100 Ω series resistor when used as output.
29	GPO17	output	General-Purpose Output Signal 17; 5V tolerant push-pull output capable of sourcing 8 mA and sinking 8 mA.
30	SCL	bidirectional	Master/Slave I2C Clock Line; 5V tolerant open-drain output with Schmitt trigger input that rejects pulses less than 5 ns.
31	SDA	bidirectional	Master/Slave I2C Data Line; 5V tolerant open-drain output with Schmitt trigger input.
32	ADC_REF	power_out	CODEC Internally Generated ADC Reference Voltage; connect via 0.1 µF ceramic and 22 µF tantalum/ceramic capacitor to AVSS.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Nuvoton Tech
Package	QFN-32-EP(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: NPCA110BA0YX
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: npca110ba0yx-etched.step / npca110ba0yx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); npca110ba0yx.step / npca110ba0yx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nuvoton Tech datasheet (30 pp, sha256 89dd1b86e8fddb6b, retrieved 2026-09-22, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF