component
NLV74HC14ADR2G
Public Made by Adomby adom
onsemi Inverters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNLV74HC14ADR2G
onsemi · Inverters · SOIC-14
NLV74HC14ADR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Schmitt-trigger inverter 1 input; unused inputs must be tied to GND or VCC. |
| 2 | Y1 | output | Inverter 1 output (Y = not A), drives 10 LSTTL loads. |
| 3 | A2 | input | Schmitt-trigger inverter 2 input; unused inputs must be tied to GND or VCC. |
| 4 | Y2 | output | Inverter 2 output (Y = not A), drives 10 LSTTL loads. |
| 5 | A3 | input | Schmitt-trigger inverter 3 input; unused inputs must be tied to GND or VCC. |
| 6 | Y3 | output | Inverter 3 output (Y = not A), drives 10 LSTTL loads. |
| 7 | GND | power_in | Ground pin (0 V reference for all voltages). |
| 8 | Y4 | output | Inverter 4 output (Y = not A), drives 10 LSTTL loads. |
| 9 | A4 | input | Schmitt-trigger inverter 4 input; unused inputs must be tied to GND or VCC. |
| 10 | Y5 | output | Inverter 5 output (Y = not A), drives 10 LSTTL loads. |
| 11 | A5 | input | Schmitt-trigger inverter 5 input; unused inputs must be tied to GND or VCC. |
| 12 | Y6 | output | Inverter 6 output (Y = not A), drives 10 LSTTL loads. |
| 13 | A6 | input | Schmitt-trigger inverter 6 input; unused inputs must be tied to GND or VCC. |
| 14 | VCC | power_in | Positive supply voltage, 2.0 to 6.0 V recommended operating range (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC Input Voltage | Vin | -0.5 | V | Max is VCC + 0.5 V; referenced to GND | 2 | ||
| DC Output Voltage | Vout | -0.5 | V | Max is VCC + 0.5 V; referenced to GND | 2 | ||
| DC Input Current, per Pin | Iin | -20 | 20 | mA | 2 | ||
| DC Output Current, per Pin | Iout | -25 | 25 | mA | 2 | ||
| DC Supply Current, VCC and GND Pins | ICC | -50 | 50 | mA | 2 | ||
| Power Dissipation in Still Air, SOIC Package | PD | 500 | mW | Derating -7 mW/°C from 65 to 125°C | 2 | ||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1 mm from case for 10 seconds, SOIC | 2 | ||
| DC Supply Voltage | VCC | 2 | 6 | V | Referenced to GND | 2 | |
| DC Input/Output Voltage | Vin, Vout | 0 | V | Max is VCC; referenced to GND | 2 | ||
| Operating Temperature Range | TA | -55 | 125 | °C | All package types | 2 | |
| Maximum Positive-Going Input Threshold Voltage | VT+ max | 3.15 | V | VCC=4.5V, Vout=0.1V, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Minimum Positive-Going Input Threshold Voltage | VT+ min | 2.3 | V | VCC=4.5V, Vout=0.1V, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Minimum Positive-Going Input Threshold Voltage | VT+ min | 2.25 | V | VCC=4.5V, Vout=0.1V, /Iout/≤20µA, ≤85°C | 3 | ||
| Maximum Negative-Going Input Threshold Voltage | VT- max | 2 | V | VCC=4.5V, Vout=VCC-0.1V, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Maximum Negative-Going Input Threshold Voltage | VT- max | 2.05 | V | VCC=4.5V, Vout=VCC-0.1V, /Iout/≤20µA, ≤85°C | 3 | ||
| Minimum Negative-Going Input Threshold Voltage | VT- min | 0.9 | V | VCC=4.5V, Vout=VCC-0.1V, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Maximum Hysteresis Voltage | VHmax | 2.25 | V | VCC=4.5V, Vout=0.1V or VCC-0.1V, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Minimum Hysteresis Voltage | VHmin | 0.4 | V | VCC=4.5V, Vout=0.1V or VCC-0.1V, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 4.4 | V | VCC=4.5V, Vin≤VT- min, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.98 | V | VCC=4.5V, Vin≤VT- min, /Iout/≤4.0mA, -55 to 25°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.84 | V | VCC=4.5V, Vin≤VT- min, /Iout/≤4.0mA, ≤85°C | 3 | ||
| Minimum High-Level Output Voltage | VOH | 3.7 | V | VCC=4.5V, Vin≤VT- min, /Iout/≤4.0mA, ≤125°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.1 | V | VCC=4.5V, Vin≥VT+ max, /Iout/≤20µA, -55 to 25°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.26 | V | VCC=4.5V, Vin≥VT+ max, /Iout/≤4.0mA, -55 to 25°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.33 | V | VCC=4.5V, Vin≥VT+ max, /Iout/≤4.0mA, ≤85°C | 3 | ||
| Maximum Low-Level Output Voltage | VOL | 0.4 | V | VCC=4.5V, Vin≥VT+ max, /Iout/≤4.0mA, ≤125°C | 3 | ||
| Maximum Input Leakage Current | Iin | -0.1 | 0.1 | µA | VCC=6.0V, Vin=VCC or GND, -55 to 25°C | 3 | |
| Maximum Input Leakage Current | Iin | -1 | 1 | µA | VCC=6.0V, Vin=VCC or GND, ≤85°C | 3 | |
| Maximum Quiescent Supply Current (per Package) | ICC | 1 | µA | VCC=6.0V, Vin=VCC or GND, Iout=0µA, -55 to 25°C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 10 | µA | VCC=6.0V, Vin=VCC or GND, Iout=0µA, ≤85°C | 3 | ||
| Maximum Quiescent Supply Current (per Package) | ICC | 40 | µA | VCC=6.0V, Vin=VCC or GND, Iout=0µA, ≤125°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 15 | ns | VCC=4.5V, CL=50pF, tr=tf=6ns, -55 to 25°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 19 | ns | VCC=4.5V, CL=50pF, tr=tf=6ns, ≤85°C | 3 | ||
| Maximum Propagation Delay, Input A to Output Y | tPLH, tPHL | 22 | ns | VCC=4.5V, CL=50pF, tr=tf=6ns, ≤125°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 15 | ns | VCC=4.5V, CL=50pF, tr=tf=6ns, -55 to 25°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 19 | ns | VCC=4.5V, CL=50pF, tr=tf=6ns, ≤85°C | 3 | ||
| Maximum Output Transition Time, Any Output | tTLH, tTHL | 22 | ns | VCC=4.5V, CL=50pF, tr=tf=6ns, ≤125°C | 3 | ||
| Maximum Input Capacitance | Cin | 10 | pF | All three temperature columns | 3 | ||
| Power Dissipation Capacitance (Per Inverter) | CPD | 22 | pF | Typical @ 25°C, VCC=5.0V | 3 |
CAD (KiCad official)
- Symbol:
NLV74HC14ADR2G - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
nlv74hc14adr2g-etched.step/nlv74hc14adr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nlv74hc14adr2g.step/nlv74hc14adr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (9 pp, sha256
c5e75b19a6aefc42, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).