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NLV74AC08DR2G

Public Made by Adom

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onsemi Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NLV74AC08DR2G

onsemi · Gates · SOIC-14

NLV74AC08DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
2 1B input Gate 1 input B, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
3 1Y output Gate 1 AND output, sources/sinks 24 mA.
4 2A input Gate 2 input A, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
5 2B input Gate 2 input B, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
6 2Y output Gate 2 AND output, sources/sinks 24 mA.
7 GND power_in Ground (0 V reference).
8 3Y output Gate 3 AND output, sources/sinks 24 mA.
9 3A input Gate 3 input A, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
10 3B input Gate 3 input B, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
11 4Y output Gate 4 AND output, sources/sinks 24 mA.
12 4A input Gate 4 input A, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
13 4B input Gate 4 input B, with input voltage range 0 to VCC (ACT version has TTL-compatible inputs).
14 VCC power_in Supply voltage: 2.0 to 6.0 V for AC, 4.5 to 5.5 V for ACT; absolute max 7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V 2
DC Input Voltage VI -0.5 V -0.5 ≤ VI ≤ VCC + 0.5 V 2
DC Output Voltage VO -0.5 V -0.5 ≤ VO ≤ VCC + 0.5 V; IO max rating must be observed 2
DC Input Diode Current IIK -20 20 mA 2
DC Output Diode Current IOK -50 50 mA 2
DC Output Sink/Source Current IO -50 50 mA 2
Storage Temperature Range TSTG -65 150 °C 2
Junction temperature under Bias TJ 150 °C 2
Thermal Resistance θJA 125 °C/W SOIC, JESD51-7 2
Power Dissipation in Still Air PD 125 mW SOIC, at 85°C 2
Latch-Up Performance ILatch-Up 100 mA Above VCC and below GND at 85°C 2
ESD Withstand Voltage HBM VESD 2000 V Human Body Model, > 2000 2
ESD Withstand Voltage CDM VESD 1000 V Charged Device Model, > 1000 2
ESD Withstand Voltage MM VESD 200 V Machine Model, > 200 2
Supply Voltage VCC 2 5 6 V 'AC 2
DC Input Voltage, Output Voltage Vin, Vout 0 V Ref. to GND; max = VCC 2
Input Rise and Fall Time tr, tf 150 ns/V 'AC, VCC @ 3.0 V 2
Input Rise and Fall Time tr, tf 40 ns/V 'AC, VCC @ 4.5 V 2
Input Rise and Fall Time tr, tf 25 ns/V 'AC, VCC @ 5.5 V 2
Operating Ambient Temperature Range TA -40 25 85 °C 2
Output Current - High IOH -24 mA 2
Output Current - Low IOL 24 mA 2
Minimum High Level Input Voltage VIH 2.1 1.5 V VCC = 3.0 V, VOUT = 0.1 V or VCC - 0.1 V, TA = +25°C 3
Minimum High Level Input Voltage VIH 3.15 2.25 V VCC = 4.5 V, VOUT = 0.1 V or VCC - 0.1 V, TA = +25°C 3
Minimum High Level Input Voltage VIH 3.85 2.75 V VCC = 5.5 V, VOUT = 0.1 V or VCC - 0.1 V, TA = +25°C 3
Maximum Low Level Input Voltage VIL 1.5 0.9 V VCC = 3.0 V, VOUT = 0.1 V or VCC - 0.1 V, TA = +25°C 3
Maximum Low Level Input Voltage VIL 2.25 1.35 V VCC = 4.5 V, VOUT = 0.1 V or VCC - 0.1 V, TA = +25°C 3
Maximum Low Level Input Voltage VIL 2.75 1.65 V VCC = 5.5 V, VOUT = 0.1 V or VCC - 0.1 V, TA = +25°C 3
Minimum High Level Output Voltage VOH 2.9 2.99 V VCC = 3.0 V, IOUT = -50 µA, TA = +25°C 3
Minimum High Level Output Voltage VOH 4.4 4.49 V VCC = 4.5 V, IOUT = -50 µA, TA = +25°C 3
Minimum High Level Output Voltage VOH 5.4 5.49 V VCC = 5.5 V, IOUT = -50 µA, TA = +25°C 3
Minimum High Level Output Voltage VOH 2.56 V VCC = 3.0 V, IOH = -12 mA, VIN = VIL or VIH, TA = +25°C 3
Minimum High Level Output Voltage VOH 3.86 V VCC = 4.5 V, IOH = -24 mA, VIN = VIL or VIH, TA = +25°C 3
Minimum High Level Output Voltage VOH 4.86 V VCC = 5.5 V, IOH = -24 mA, VIN = VIL or VIH, TA = +25°C 3
Maximum Low Level Output Voltage VOL 0.36 V VCC = 3.0 V, IOL = 12 mA, VIN = VIL or VIH, TA = +25°C 3
Maximum Input Leakage Current IIN -0.1 0.1 µA VI = VCC, GND, VCC = 5.5 V, TA = +25°C 3
Maximum Input Leakage Current IIN -1 1 µA VI = VCC, GND, VCC = 5.5 V, TA = -40°C to +85°C 3
Minimum Dynamic Output Current IOLD 75 mA VOLD = 1.65 V Max, VCC = 5.5 V 3
Minimum Dynamic Output Current IOHD -75 mA VOHD = 3.85 V Min, VCC = 5.5 V 3
Maximum Quiescent Supply Current ICC 4 µA VIN = VCC or GND, VCC = 5.5 V, TA = +25°C 3
Maximum Quiescent Supply Current ICC 40 µA VIN = VCC or GND, VCC = 5.5 V, TA = -40°C to +85°C 3
Propagation Delay tPLH 1.5 7.5 9.5 ns VCC = 3.3 V, TA = +25°C, CL = 50 pF 3
Propagation Delay tPLH 1 10 ns VCC = 3.3 V, TA = -40°C to +85°C, CL = 50 pF 3
Propagation Delay tPLH 1.5 5.5 7.5 ns VCC = 5.0 V, TA = +25°C, CL = 50 pF 3
Propagation Delay tPLH 1 8.5 ns VCC = 5.0 V, TA = -40°C to +85°C, CL = 50 pF 3
Propagation Delay tPHL 1.5 7 8.5 ns VCC = 3.3 V, TA = +25°C, CL = 50 pF 3
Propagation Delay tPHL 1 9 ns VCC = 3.3 V, TA = -40°C to +85°C, CL = 50 pF 3
Propagation Delay tPHL 1.5 5.5 7 ns VCC = 5.0 V, TA = +25°C, CL = 50 pF 3
Propagation Delay tPHL 1 7.5 ns VCC = 5.0 V, TA = -40°C to +85°C, CL = 50 pF 3
Input Capacitance CIN 4.5 pF VCC = 5.0 V 4
Power Dissipation Capacitance CPD 20 pF VCC = 5.0 V 4

CAD (KiCad official)

  • Symbol: NLV74AC08DR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: nlv74ac08dr2g-etched.step / nlv74ac08dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nlv74ac08dr2g.step / nlv74ac08dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 c7bfdba597765f9e, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF