component

NLV14175BDR2G

Public Made by Adom

by adom

onsemi Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icsnlv14175bdr2gfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
nlv14175bdr2g / README.md
History Download
Ray Publish 0.1.0 c1bab02 7d ago

NLV14175BDR2G

onsemi · Flip Flops · SOIC-16

NLV14175BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R input Active-low asynchronous reset input that resets all four flip-flops (Q low, Q-bar high).
2 Q0 output True output of flip-flop 0, compatible with two low-power TTL loads.
3 ~{Q0} output Complementary output of flip-flop 0.
4 D0 input Data input of flip-flop 0, sampled on the positive clock edge.
5 D1 input Data input of flip-flop 1, sampled on the positive clock edge.
6 ~{Q1} output Complementary output of flip-flop 1.
7 Q1 output True output of flip-flop 1.
8 VSS power_in Negative supply (ground); voltages are referenced to VSS.
9 C input Common positive-edge-triggered clock input for all four flip-flops.
10 Q2 output True output of flip-flop 2.
11 ~{Q2} output Complementary output of flip-flop 2.
12 D2 input Data input of flip-flop 2, sampled on the positive clock edge.
13 D3 input Data input of flip-flop 3, sampled on the positive clock edge.
14 ~{Q3} output Complementary output of flip-flop 3.
15 Q3 output True output of flip-flop 3.
16 VDD power_in Positive supply, 3.0 Vdc to 18 Vdc (absolute maximum -0.5 to +18.0 V).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range VDD -0.5 18 V Referenced to VSS 1
Input or Output Voltage Range (DC or Transient) Vin, Vout -0.5 V Max printed as VDD + 0.5 1
Input or Output Current per Pin Iin, Iout -10 10 mA DC or Transient 1
Power Dissipation per Package PD 500 mW Note 1: derate -7.0 mW/C from 65C to 125C 1
Ambient Temperature Range TA -55 125 °C 1
Storage Temperature Range Tstg -65 150 °C 1
Lead Temperature 260 °C 8-Second Soldering 1
Supply Voltage Range VDD 3 18 Vdc Features 1
Output Voltage 0 Level VOL 0 0.05 Vdc VDD=5.0 V, Vin=VDD or 0, 25C 3
Output Voltage 1 Level VOH 4.95 5 Vdc VDD=5.0 V, Vin=0 or VDD, 25C 3
Output Voltage 1 Level VOH 9.95 10 Vdc VDD=10 V, Vin=0 or VDD, 25C 3
Output Voltage 1 Level VOH 14.95 15 Vdc VDD=15 V, Vin=0 or VDD, 25C 3
Input Voltage 0 Level VIL 2.25 1.5 Vdc VDD=5.0 V, VO=4.5 or 0.5 Vdc, 25C 3
Input Voltage 0 Level VIL 4.5 3 Vdc VDD=10 V, VO=9.0 or 1.0 Vdc, 25C 3
Input Voltage 0 Level VIL 6.75 4 Vdc VDD=15 V, VO=13.5 or 1.5 Vdc, 25C 3
Input Voltage 1 Level VIH 3.5 2.75 Vdc VDD=5.0 V, VO=0.5 or 4.5 Vdc, 25C 3
Input Voltage 1 Level VIH 7 5.5 Vdc VDD=10 V, VO=1.0 or 9.0 Vdc, 25C 3
Input Voltage 1 Level VIH 11 8.25 Vdc VDD=15 V, VO=1.5 or 13.5 Vdc, 25C 3
Output Drive Current Source IOH -2.4 -4.2 mAdc VDD=5.0 V, VOH=2.5 Vdc, 25C 3
Output Drive Current Source IOH -0.51 -0.88 mAdc VDD=5.0 V, VOH=4.6 Vdc, 25C 3
Output Drive Current Source IOH -1.3 -2.25 mAdc VDD=10 V, VOH=9.5 Vdc, 25C 3
Output Drive Current Source IOH -3.4 -8.8 mAdc VDD=15 V, VOH=13.5 Vdc, 25C 3
Output Drive Current Sink IOL 0.51 0.88 mAdc VDD=5.0 V, VOL=0.4 Vdc, 25C 3
Output Drive Current Sink IOL 1.3 2.25 mAdc VDD=10 V, VOL=0.5 Vdc, 25C 3
Output Drive Current Sink IOL 3.4 8.8 mAdc VDD=15 V, VOL=1.5 Vdc, 25C 3
Input Current Iin -0.1 1e-05 0.1 µAdc VDD=15 V, 25C 3
Input Capacitance Cin 5 7.5 pF Vin = 0, 25C 3
Quiescent Current (Per Package) IDD 0.005 5 µAdc VDD=5.0 V, 25C 3
Quiescent Current (Per Package) IDD 0.01 10 µAdc VDD=10 V, 25C 3
Quiescent Current (Per Package) IDD 0.015 20 µAdc VDD=15 V, 25C 3
Quiescent Current (Per Package) IDD 150 µAdc VDD=5.0 V, 125C 3
Quiescent Current (Per Package) IDD 300 µAdc VDD=10 V, 125C 3
Quiescent Current (Per Package) IDD 600 µAdc VDD=15 V, 125C 3
Output Rise and Fall Time tTLH, tTHL 100 200 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Output Rise and Fall Time tTLH, tTHL 50 100 ns VDD=10 V, CL=50 pF, TA=25C 4
Output Rise and Fall Time tTLH, tTHL 40 80 ns VDD=15 V, CL=50 pF, TA=25C 4
Propagation Delay Time Clock to Q, Q tPLH, tPHL 220 400 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Propagation Delay Time Clock to Q, Q tPLH, tPHL 90 160 ns VDD=10 V, CL=50 pF, TA=25C 4
Propagation Delay Time Clock to Q, Q tPLH, tPHL 70 120 ns VDD=15 V, CL=50 pF, TA=25C 4
Propagation Delay Time Reset to Q, Q tPHL, tPLH 325 500 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Clock Pulse Width tWH 250 110 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Clock Pulse Width tWH 100 45 ns VDD=10 V, CL=50 pF, TA=25C 4
Clock Pulse Width tWH 75 35 ns VDD=15 V, CL=50 pF, TA=25C 4
Reset Pulse Width tWL 200 100 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Reset Pulse Width tWL 80 40 ns VDD=10 V, CL=50 pF, TA=25C 4
Reset Pulse Width tWL 60 30 ns VDD=15 V, CL=50 pF, TA=25C 4
Data Setup Time tsu 120 60 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Data Setup Time tsu 50 25 ns VDD=10 V, CL=50 pF, TA=25C 4
Data Setup Time tsu 40 20 ns VDD=15 V, CL=50 pF, TA=25C 4
Data Hold Time th 80 40 ns VDD=5.0 V, CL=50 pF, TA=25C 4
Reset Removal Time trem 250 125 ns VDD=5.0 V, CL=50 pF, TA=25C 4

CAD (KiCad official)

  • Symbol: NLV14175BDR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: nlv14175bdr2g-etched.step / nlv14175bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nlv14175bdr2g.step / nlv14175bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (6 pp, sha256 f6268e08a8e5eb8f, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF