component

NLV14044BDR2G

Public Made by Adom

by adom

onsemi Latches, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icsnlv14044bdr2gfactory-2.0.0extractor-text

Verified NLV14044BDR2G

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: NLV14044BDR2G · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 7-page datasheet
  • ✓distributor: lcsc C604199, digikey 488-NLV14044BDR2GTR-ND, mouser 863-NLV14044BDR2G
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-86hwoq4r/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.6)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ nlv14044bdr2g.kicad_sym✓ nlv14044bdr2g.kicad_mod✓ nlv14044bdr2g.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

NLV14044BDR2G

onsemi · Latches · SOIC-16

NLV14044BDR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q3 tri_state Three-state Q output of latch 3, open circuit when ENABLE is low.
2 NC unconnected No connection.
3 S0 input Active-low set input of latch 0; unused inputs must be tied to VSS or VDD.
4 R0 input Active-low reset input of latch 0; unused inputs must be tied to VSS or VDD.
5 E input Common output enable; a logic high enables the Q outputs and a logic low puts them in high impedance.
6 R1 input Active-low reset input of latch 1; unused inputs must be tied to VSS or VDD.
7 S1 input Active-low set input of latch 1; unused inputs must be tied to VSS or VDD.
8 VSS power_in Ground reference (VSS) for all voltages.
9 Q1 tri_state Three-state Q output of latch 1, open circuit when ENABLE is low.
10 Q2 tri_state Three-state Q output of latch 2, open circuit when ENABLE is low.
11 S2 input Active-low set input of latch 2; unused inputs must be tied to VSS or VDD.
12 R2 input Active-low reset input of latch 2; unused inputs must be tied to VSS or VDD.
13 Q0 tri_state Three-state Q output of latch 0, open circuit when ENABLE is low.
14 R3 input Active-low reset input of latch 3; unused inputs must be tied to VSS or VDD.
15 S3 input Active-low set input of latch 3; unused inputs must be tied to VSS or VDD.
16 VDD power_in Positive supply, 3.0 Vdc to 18 Vdc operating range, absolute maximum -0.5 to +18.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range VDD -0.5 18 V Voltages referenced to VSS 1
Input or Output Voltage Range (DC or Transient) Vin, Vout -0.5 V Max printed as VDD + 0.5 V (not numeric) 1
Input or Output Current (DC or Transient) per Pin Iin, Iout -10 10 mA Per pin; printed as ±10 mA 1
Power Dissipation, per Package PD 500 mW Note 1: -7.0 mW/C from 65C to 125C for D/DW packages 1
Ambient Temperature Range TA -55 125 °C 1
Storage Temperature Range Tstg -65 150 °C 1
Lead Temperature TL 260 °C 8-second soldering 1
Supply Voltage Range VDD 3 18 Vdc Printed in Features list: Supply Voltage Range = 3.0 Vdc to 18 Vdc 1
Output Voltage '0' Level VOL 0 0.05 Vdc VDD = 5.0 Vdc; Vin = VDD or 0; limit at -55C, 25C, 125C; typ at 25C 3
Output Voltage '1' Level VOH 4.95 5 Vdc VDD = 5.0 Vdc; Vin = 0 or VDD; limit at -55C, 25C, 125C; typ at 25C 3
Output Voltage '1' Level VOH 9.95 10 Vdc VDD = 10 Vdc; Vin = 0 or VDD; limit at -55C, 25C, 125C; typ at 25C 3
Output Voltage '1' Level VOH 14.95 15 Vdc VDD = 15 Vdc; Vin = 0 or VDD; limit at -55C, 25C, 125C; typ at 25C 3
Input Voltage '0' Level VIL 2.25 1.5 Vdc VDD = 5.0 Vdc; VO = 4.5 or 0.5 Vdc; limit at -55C, 25C, 125C; typ at 25C 3
Input Voltage '0' Level VIL 4.5 3 Vdc VDD = 10 Vdc; VO = 9.0 or 1.0 Vdc; limit at -55C, 25C, 125C; typ at 25C 3
Input Voltage '0' Level VIL 6.75 4 Vdc VDD = 15 Vdc; VO = 13.5 or 1.5 Vdc; limit at -55C, 25C, 125C; typ at 25C 3
Input Voltage '1' Level VIH 3.5 2.75 Vdc VDD = 5.0 Vdc; VO = 0.5 or 4.5 Vdc; limit at -55C, 25C, 125C; typ at 25C 3
Input Voltage '1' Level VIH 7 5.5 Vdc VDD = 10 Vdc; VO = 1.0 or 9.0 Vdc; limit at -55C, 25C, 125C; typ at 25C 3
Input Voltage '1' Level VIH 11 8.25 Vdc VDD = 15 Vdc; VO = 1.5 or 13.5 Vdc; limit at -55C, 25C, 125C; typ at 25C 3
Output Drive Current (Source) IOH -2.4 -4.2 mAdc VDD = 5.0 Vdc; VOH = 2.5 Vdc; 25C column 3
Output Drive Current (Source) IOH -0.51 -0.88 mAdc VDD = 5.0 Vdc; VOH = 4.6 Vdc; 25C column 3
Output Drive Current (Source) IOH -1.3 -2.25 mAdc VDD = 10 Vdc; VOH = 9.5 Vdc; 25C column 3
Output Drive Current (Source) IOH -3.4 -8.8 mAdc VDD = 15 Vdc; VOH = 13.5 Vdc; 25C column 3
Output Drive Current (Sink) IOL 0.51 0.88 mAdc VDD = 5.0 Vdc; VOL = 0.4 Vdc; 25C column 3
Output Drive Current (Sink) IOL 1.3 2.25 mAdc VDD = 10 Vdc; VOL = 0.5 Vdc; 25C column 3
Output Drive Current (Sink) IOL 3.4 8.8 mAdc VDD = 15 Vdc; VOL = 1.5 Vdc; 25C column 3
Quiescent Current (Per Package) IDD 0.002 1 Adc VDD = 5.0 Vdc; limit at -55C and 25C; typ at 25C 3
Quiescent Current (Per Package) IDD 0.004 2 Adc VDD = 10 Vdc; limit at -55C and 25C; typ at 25C 3
Quiescent Current (Per Package) IDD 0.006 4 Adc VDD = 15 Vdc; limit at -55C and 25C; typ at 25C 3
Quiescent Current (Per Package) IDD 30 Adc VDD = 5.0 Vdc; TA = 125C 3
Quiescent Current (Per Package) IDD 60 Adc VDD = 10 Vdc; TA = 125C 3
Quiescent Current (Per Package) IDD 120 Adc VDD = 15 Vdc; TA = 125C 3
Input Current Iin -0.1 0.1 Adc VDD = 15 Vdc; TA = -55C and 25C 3
Input Current Iin -1 1 Adc VDD = 15 Vdc; TA = 125C 3
Three-State Output Leakage Current ITL -0.1 0.1 Adc VDD = 15 Vdc; TA = -55C and 25C 3
Three-State Output Leakage Current ITL -3 3 Adc VDD = 15 Vdc; TA = 125C 3
Input Capacitance Cin 5 7.5 pF Vin = 0 3
Output Rise Time tTLH 100 200 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Output Rise Time tTLH 50 100 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Output Rise Time tTLH 40 80 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4
Output Fall Time tTHL 100 200 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Output Fall Time tTHL 50 100 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Output Fall Time tTHL 40 80 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4
Propagation Delay Time (Low-to-High) tPLH 175 350 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Propagation Delay Time (Low-to-High) tPLH 75 175 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Propagation Delay Time (Low-to-High) tPLH 60 120 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4
Propagation Delay Time (High-to-Low) tPHL 175 350 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Propagation Delay Time (High-to-Low) tPHL 75 175 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Propagation Delay Time (High-to-Low) tPHL 60 120 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4
Set Pulse Width tW 200 80 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Set Pulse Width tW 100 40 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Set Pulse Width tW 70 30 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4
Reset Pulse Width tW 200 80 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Reset Pulse Width tW 100 40 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Reset Pulse Width tW 70 30 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4
Three-State Enable/Disable Delay tPLZ, tPHZ, tPZL, tPZH 150 300 ns VDD = 5.0 Vdc; CL = 50 pF, TA = 25C 4
Three-State Enable/Disable Delay tPLZ, tPHZ, tPZL, tPZH 80 160 ns VDD = 10 Vdc; CL = 50 pF, TA = 25C 4
Three-State Enable/Disable Delay tPLZ, tPHZ, tPZL, tPZH 55 110 ns VDD = 15 Vdc; CL = 50 pF, TA = 25C 4

CAD (KiCad official)

  • Symbol: NLV14044BDR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: nlv14044bdr2g-etched.step / nlv14044bdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nlv14044bdr2g.step / nlv14044bdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (7 pp, sha256 72f3daa0afff15a9, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF