# NLSF595DTR2G

**onsemi** · LED Drivers · TSSOP-16

NLSF595DTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QB | output | Parallel open-drain output QB, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 2 | QC | output | Parallel open-drain output QC, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 3 | QD | output | Parallel open-drain output QD, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 4 | QE | output | Parallel open-drain output QE, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 5 | QF | output | Parallel open-drain output QF, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 6 | QG | output | Parallel open-drain output QG, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 7 | QH | output | Parallel open-drain output QH, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 8 | GND | power_in | Ground reference for the device. |
| 9 | SQH | output | Standard CMOS serial data output of the shift register, used to cascade more than one device. |
| 10 | SCLR | input | Active-low shift register reset; driving it low clears the shift register. |
| 11 | SCK | input | Shift clock; serial data on SI is shifted into the shift register on its low-to-high edge, with Fmax above 25 MHz. |
| 12 | RCK | input | Register clock; a low-to-high transition transfers the shift register contents to the storage register that drives the parallel outputs. |
| 13 | OE | input | Active-low output enable; driving it high forces QA-QH into the high-impedance state, and it may be permanently pulled low. |
| 14 | SI | input | Serial data input, CMOS-level compatible, with overvoltage protection up to 7.0 V. |
| 15 | QA | output | Parallel open-drain output QA, capable of sinking more than 12 mA and withstanding up to 7.0 V regardless of VCC. |
| 16 | VCC | power_in | Positive supply, specified from 2.0 V to 5.5 V; pins tolerate voltages up to 7.0 V above VCC without damage. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | LED Drivers |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive DC Supply Voltage | VCC | -0.5 |  | 7 | V |  | 4 |
| Digital Input Voltage | VIN | -0.5 |  | 7 | V |  | 4 |
| DC Output Voltage | VOUT | -0.5 |  |  | V | upper limit printed as VCC +7.0 | 4 |
| Input Diode Current | IIK | -20 |  |  | mA | single value printed as -20 mA | 4 |
| Output Diode Current | IOK | -50 |  | 50 | mA | printed as ±50 mA | 4 |
| DC Output Current, per Pin | IOUT |  |  | 50 | mA |  | 4 |
| DC Supply Current, VCC and GND Pins | ICC | -75 |  | 75 | mA | printed as ±75 mA | 4 |
| Power Dissipation in Still Air | PD |  |  | 450 | mW | still air | 4 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 4 |
| Latchup Performance | ILATCHUP | -300 |  | 300 | mA | Above VCC and Below GND at 125°C (Note 1) | 4 |
| DC Supply Voltage | VCC | 2 |  | 5.5 | V |  | 4 |
| DC Input Voltage | VIN | 0 |  | 5.5 | V |  | 4 |
| DC Output Voltage | VOUT | 0 |  |  | V | upper limit printed as VCC | 4 |
| Operating Temperature Range, all Package Types | TA | -55 |  | 125 | °C |  | 4 |
| Input Rise or Fall Time | tr, tf | 0 |  | 50 | ns/V | VCC = 3.3 V ± 0.3 V | 4 |
| Input Rise or Fall Time | tr, tf | 0 |  | 15 | ns/V | VCC = 5.0 V ± 0.5 V | 4 |
| Minimum High-Level Input Voltage | VIH | 1.5 |  |  | V | VCC = 2.0 V; TA = 25°C | 5 |
| Minimum High-Level Input Voltage | VIH | 2.1 |  |  | V | VCC = 3.0 V; TA = 25°C | 5 |
| Minimum High-Level Input Voltage | VIH | 3.15 |  |  | V | VCC = 4.5 V; TA = 25°C | 5 |
| Minimum High-Level Input Voltage | VIH | 3.85 |  |  | V | VCC = 5.5 V; TA = 25°C | 5 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.59 | V | VCC = 2.0 V; TA = 25°C | 5 |
| Maximum Low-Level Input Voltage | VIL |  |  | 0.9 | V | VCC = 3.0 V; TA = 25°C | 5 |
| Maximum Low-Level Input Voltage | VIL |  |  | 1.35 | V | VCC = 4.5 V; TA = 25°C | 5 |
| Maximum Low-Level Input Voltage | VIL |  |  | 1.65 | V | VCC = 5.5 V; TA = 25°C | 5 |
| Minimum High-Level Serial Output Voltage | VOH | 1.9 |  |  | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 2.0 V; TA = 25°C | 5 |
| Minimum High-Level Serial Output Voltage | VOH | 2.9 |  |  | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 3.0 V; TA = 25°C | 5 |
| Minimum High-Level Serial Output Voltage | VOH | 4.4 |  |  | V | VIN = VIH or VIL; IOH = −50 µA; VCC = 4.5 V; TA = 25°C | 5 |
| Minimum High-Level Output Voltage | VOH | 2.58 |  |  | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 3.0 V; TA = 25°C | 5 |
| Minimum High-Level Output Voltage | VOH | 3.94 |  |  | V | VIN = VIH or VIL; IOH = −8 mA; VCC = 4.5 V; TA = 25°C | 5 |
| Maximum Low-Level Output Voltage | VOL |  | 0 | 0.1 | V | VIN = VIH or VIL; IOL = 50 µA; VCC = 2.0 V; TA = 25°C | 5 |
| Maximum Low-Level Output Voltage | VOL |  |  | 0.36 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 3.0 V; TA = 25°C | 5 |
| Maximum Input Leakage Current | IIN | -0.1 |  | 0.1 | µA | VIN = 5.5 V or GND; VCC = 0 to 5.5 V; TA = 25°C | 5 |
| Maximum Input Leakage Current | IIN | -1 |  | 1 | µA | VIN = 5.5 V or GND; VCC = 0 to 5.5 V; TA = 125°C | 5 |
| Maximum Quiescent Supply Current | ICC |  |  | 4 | µA | VIN = VCC or GND; VCC = 5.5 V; TA = 25°C | 5 |
| Maximum Quiescent Supply Current | ICC |  |  | 40 | µA | VIN = VCC or GND; VCC = 5.5 V; TA = 125°C | 5 |
| Three-State Output Off-State Current QA−QH | IOZ | -0.25 |  | 0.25 | µA | VIN = VIH or VIL; VOUT = VCC or GND; VCC = 5.5 V; TA = 25°C | 5 |
| Three-State Output Off-State Current QA−QH | IOZ | -2.5 |  | 2.5 | µA | VIN = VIH or VIL; VOUT = VCC or GND; VCC = 5.5 V; TA = 125°C | 5 |
| Active (2) State Off Output Leakage Current QA−QH | ILKG | -0.25 |  | 0.25 | µA | VIN = VIH or VIL; VOUT = VCC or GND; VCC = 5.5 V; TA = 25°C | 5 |
| Active (2) State Off Output Leakage Current QA−QH | ILKG | -2.5 |  | 2.5 | µA | VIN = VIH or VIL; VOUT = VCC or GND; VCC = 5.5 V; TA = 125°C | 5 |
| Power Off Output Leakage All Outputs | IOFF | -0.25 |  | 0.25 | µA | VIN = 0 or 5.5 V; VOUT = 5.5 V; VCC = 0 V; TA = 25°C | 5 |
| Power Off Output Leakage All Outputs | IOFF | -2.5 |  | 2.5 | µA | VIN = 0 or 5.5 V; VOUT = 5.5 V; VCC = 0 V; TA = 125°C | 5 |
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 80 |  | 150 | MHz | VCC = 3.3 ± 0.3 V; TA = 25°C | 6 |
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 70 |  |  | MHz | VCC = 3.3 ± 0.3 V; TA = 125°C | 6 |
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 135 |  | 185 | MHz | VCC = 5.0 ± 0.5 V; TA = 25°C | 6 |
| Maximum Clock Frequency (50% Duty Cycle) | fmax | 115 |  |  | MHz | VCC = 5.0 ± 0.5 V; TA = 125°C | 6 |
| Input Capacitance | CIN |  | 4 | 10 | pF |  | 6 |
| Three-State Output Capacitance QA−QH | COUT |  | 6 | 10 | pF | Output in high-impedance state | 6 |
| Quiet Output Maximum Dynamic VOL | VOLP |  | 0.8 | 1 | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 6 |
| Quiet Output Minimum Dynamic VOL | VOLV |  | -0.8 | -1 | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 6 |
| Minimum High Level Dynamic Input Voltage | VIHD | 3.5 |  |  | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 6 |
| Maximum Low Level Dynamic Input Voltage | VILD |  |  | 1.5 | V | Input tr = tf = 3.0 ns; CL = 50 pF; VCC = 5.0 V; TA = 25°C | 6 |
| Setup Time, SI to SCK | tsu | 3.5 |  |  | ns | Input tr = tf = 3.0 ns; VCC = 3.3 V; TA = 25°C | 7 |
| Setup Time, SI to SCK | tsu | 3 |  |  | ns | Input tr = tf = 3.0 ns; VCC = 5.0 V; TA = 25°C | 7 |
| Hold Time, SI to SCK | th | 1.5 |  |  | ns | Input tr = tf = 3.0 ns; VCC = 3.3 V; TA = 25°C | 7 |
| Hold Time, SI to SCK | th | 2 |  |  | ns | Input tr = tf = 3.0 ns; VCC = 5.0 V; TA = 25°C | 7 |
| Thermal Resistance, Junction-to-Ambient | JA |  | 128 |  | °C/W |  | 4 |

## CAD (KiCad official)

- Symbol: `NLSF595DTR2G`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `nlsf595dtr2g-etched.step` / `nlsf595dtr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nlsf595dtr2g.step` / `nlsf595dtr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588948280109092864) (15 pp, sha256 `5cabe999a3becec8`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/nlsf595dtr2g-datasheet.pdf)