← Commit history

Publish 0.2.0

Ray ·e332df25cb · ·parent 3c9b003
3 files changed +26−12
README.md+14
@@ -36,6 +36,20 @@ NL27WZ04DFT2G from onsemi, in a SC-70-6(SOT-363). Pinout and pin descriptions ex - Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6` - 3D model: SC-70-6(SOT-363) (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`nl27wz04dft2g.step`](nl27wz04dft2g.step) | 99 KB | You want the bare part, or you mark your own boards. |+| [`nl27wz04dft2g-etched.step`](nl27wz04dft2g-etched.step) | 2.0 MB | You want the part with `NL27WZ04DFT2G` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 510 faces against 117 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1
@@ -1,6 +1,6 @@ {   "slug": "nl27wz04dft2g",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "onsemi Inverters, SC-70-6(SOT-363). Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [
page.json+11−11
@@ -4,7 +4,7 @@   "slug": "nl27wz04dft2g",   "title": "NL27WZ04DFT2G",   "brief": "onsemi Inverters, SC-70-6(SOT-363). Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -34,37 +34,37 @@         "number": "1",         "name": "IN A1",         "type": "input",-        "description": "Logic input to inverter 1. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7\u00b7VCC (0.75\u00b7VCC below 2.3 V VCC), VIL = 0.3\u00b7VCC. Tolerates up to 5.5 V regardless of VCC."+        "description": "Logic input to inverter 1. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC."       },       {         "number": "2",         "name": "GND",         "type": "power_in",-        "description": "Ground reference (0 V). Maximum DC ground current per pin is \u00b1100 mA."+        "description": "Ground reference (0 V). Maximum DC ground current per pin is ±100 mA."       },       {         "number": "3",         "name": "IN A2",         "type": "input",-        "description": "Logic input to inverter 2. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7\u00b7VCC (0.75\u00b7VCC below 2.3 V VCC), VIL = 0.3\u00b7VCC. Tolerates up to 5.5 V regardless of VCC."+        "description": "Logic input to inverter 2. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC."       },       {         "number": "4",         "name": "OUT Y2",         "type": "output",-        "description": "Inverted logic output of inverter 2 (Y2 = /A2). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH \u2248 VCC\u22120.1 V and VOL \u2248 0.1 V at 100 \u00b5A load."+        "description": "Inverted logic output of inverter 2 (Y2 = /A2). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply. Operating range 1.65 V to 5.5 V (1.5 V min for data retention only). Recommend local 0.1 \u00b5F decoupling to GND."+        "description": "Positive supply. Operating range 1.65 V to 5.5 V (1.5 V min for data retention only). Recommend local 0.1 µF decoupling to GND."       },       {         "number": "6",         "name": "OUT Y1",         "type": "output",-        "description": "Inverted logic output of inverter 1 (Y1 = /A1). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH \u2248 VCC\u22120.1 V and VOL \u2248 0.1 V at 100 \u00b5A load."+        "description": "Inverted logic output of inverter 1 (Y1 = /A1). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load."       }     ],     "provenance": {@@ -138,9 +138,9 @@     "docs/hero.png",     "docs/nl27wz04dft2g-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "onsemi Inverters, SC-70-6(SOT-363). Datasheet-verified pinout, KiCad symbol/footprint/3D." }\ No newline at end of file