component
NL27WZ04DFT2G
Public Made by Adomby adom
onsemi Inverters, SC-70-6(SOT-363). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C154778). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+37−17
nl27wz04dft2g.lbr+28−10@@ -60,6 +60,18 @@ <smd name="4" x="0.8375" y="-0.6500" dx="1.0250" dy="0.3500" layer="1"/> <smd name="5" x="0.8375" y="-0.0000" dx="1.0250" dy="0.3500" layer="1"/> <smd name="6" x="0.8375" y="0.6500" dx="1.0250" dy="0.3500" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.1800" y="1.0900"/>+ <vertex x="-1.3200" y="1.2800"/>+ <vertex x="-1.0400" y="1.2800"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.3125" y="1.0000"/>+ <vertex x="0.6250" y="1.0000"/>+ <vertex x="0.6250" y="-1.0000"/>+ <vertex x="-0.6250" y="-1.0000"/>+ <vertex x="-0.6250" y="0.6875"/>+ </polygon> <wire x1="-0.7350" y1="1.1100" x2="0.7350" y2="1.1100" width="0.1200" layer="21"/> <wire x1="-0.7350" y1="1.0850" x2="-0.7350" y2="1.1100" width="0.1200" layer="21"/> <wire x1="-0.7350" y1="-1.1100" x2="-0.7350" y2="-1.0850" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.7350" y1="-1.1100" x2="-0.7350" y2="-1.1100" width="0.1200" layer="21"/> <text x="0" y="1.763" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-1.763" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.1800" y="1.0900"/><vertex x="-1.3200" y="1.2800"/><vertex x="-1.0400" y="1.2800"/></polygon></package>+</package> </packages> <symbols> <symbol name="NL27WZ04DFT2G">@@ -78,12 +90,12 @@ <wire x1="-12.7" y1="-5.08" x2="-12.7" y2="5.08" width="0.254" layer="94"/> <text x="0" y="7.62" size="1.27" layer="95" align="bottom-center">>NAME</text> <text x="0" y="-7.62" size="1.27" layer="96" align="top-center">>VALUE</text>- <pin name="IN A1" x="-17.78" y="2.54" length="middle" direction="in"/>+ <pin name="IN_A1" x="-17.78" y="2.54" length="middle" direction="in"/> <pin name="GND" x="-17.78" y="0" length="middle" direction="pwr"/>- <pin name="IN A2" x="-17.78" y="-2.54" length="middle" direction="in"/>- <pin name="OUT Y1" x="17.78" y="2.54" length="middle" direction="out" rot="R180"/>+ <pin name="IN_A2" x="-17.78" y="-2.54" length="middle" direction="in"/>+ <pin name="OUT_Y1" x="17.78" y="2.54" length="middle" direction="out" rot="R180"/> <pin name="VCC" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/>- <pin name="OUT Y2" x="17.78" y="-2.54" length="middle" direction="out" rot="R180"/>+ <pin name="OUT_Y2" x="17.78" y="-2.54" length="middle" direction="out" rot="R180"/> </symbol> </symbols> <devicesets>@@ -95,14 +107,20 @@ <devices> <device name="" package="NL27WZ04DFT2G"> <connects>- <connect gate="G$1" pin="IN A1" pad="1"/>+ <connect gate="G$1" pin="IN_A1" pad="1"/> <connect gate="G$1" pin="GND" pad="2"/>- <connect gate="G$1" pin="IN A2" pad="3"/>- <connect gate="G$1" pin="OUT Y1" pad="6"/>+ <connect gate="G$1" pin="IN_A2" pad="3"/>+ <connect gate="G$1" pin="OUT_Y1" pad="6"/> <connect gate="G$1" pin="VCC" pad="5"/>- <connect gate="G$1" pin="OUT Y2" pad="4"/>+ <connect gate="G$1" pin="OUT_Y2" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="NL27WZ04DFT2G" constant="no"/>+ <attribute name="MANUFACTURER" value="onsemi" constant="no"/>+ <attribute name="LCSC_PN" value="C154778" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>
page.json+9−7@@ -26,43 +26,45 @@ "model_3d_step": "nl27wz04dft2g.step", "lbr": "nl27wz04dft2g.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C154778"+ }, "pins": [ { "number": "1", "name": "IN A1", "type": "input",- "description": "Logic input to inverter 1. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC."+ "description": "Logic input to inverter 1. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7\u00b7VCC (0.75\u00b7VCC below 2.3 V VCC), VIL = 0.3\u00b7VCC. Tolerates up to 5.5 V regardless of VCC." }, { "number": "2", "name": "GND", "type": "power_in",- "description": "Ground reference (0 V). Maximum DC ground current per pin is ±100 mA."+ "description": "Ground reference (0 V). Maximum DC ground current per pin is \u00b1100 mA." }, { "number": "3", "name": "IN A2", "type": "input",- "description": "Logic input to inverter 2. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC."+ "description": "Logic input to inverter 2. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7\u00b7VCC (0.75\u00b7VCC below 2.3 V VCC), VIL = 0.3\u00b7VCC. Tolerates up to 5.5 V regardless of VCC." }, { "number": "4", "name": "OUT Y2", "type": "output",- "description": "Inverted logic output of inverter 2 (Y2 = /A2). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load."+ "description": "Inverted logic output of inverter 2 (Y2 = /A2). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH \u2248 VCC\u22120.1 V and VOL \u2248 0.1 V at 100 \u00b5A load." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply. Operating range 1.65 V to 5.5 V (1.5 V min for data retention only). Recommend local 0.1 µF decoupling to GND."+ "description": "Positive supply. Operating range 1.65 V to 5.5 V (1.5 V min for data retention only). Recommend local 0.1 \u00b5F decoupling to GND." }, { "number": "6", "name": "OUT Y1", "type": "output",- "description": "Inverted logic output of inverter 1 (Y1 = /A1). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load."+ "description": "Inverted logic output of inverter 1 (Y1 = /A1). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH \u2248 VCC\u22120.1 V and VOL \u2248 0.1 V at 100 \u00b5A load." } ], "provenance": {