component

NL17SZ17DFT2G

Public Made by Adom

by adom

onsemi Buffer/Driver/Transceiver, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogicnl17sz17dft2g
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs nl17sz17dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
nl17sz17dft2g-etched.fit.json nl17sz17dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nl17sz17dft2g-etched.glb nl17sz17dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nl17sz17dft2g-etched.step nl17sz17dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nl17sz17dft2g.glb Publish 0.1.0 · Ray
nl17sz17dft2g.kicad_mod Publish 0.1.0 · Ray
nl17sz17dft2g.kicad_sym Publish 0.1.0 · Ray
nl17sz17dft2g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
nl17sz17dft2g.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json nl17sz17dft2g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md nl17sz17dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray

NL17SZ17DFT2G

onsemi · Buffer/Driver/Transceiver · SC-70-5

NL17SZ17DFT2G from onsemi, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection. Leave floating or tie as convenient for layout.
2 A input Schmitt-trigger logic input. Threshold hysteresis is typ 0.93 V at VCC = 3.0 V. Input is overvoltage tolerant up to 5.5 V regardless of VCC.
3 GND power_in Ground reference (0 V) for the buffer.
4 Y output Non-inverting buffered logic output (Y = A). Rail-to-rail CMOS drive capable of ±24 mA at VCC = 3.0 V.
5 VCC power_in Positive supply, 1.65 V to 5.5 V. Bypass with a ~100 nF ceramic capacitor close to the pin. Quiescent supply current ICC ≤ 1 µA typical.

Key specifications

Parameter Value
Manufacturer onsemi
Package SC-70-5
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • NL17SZ17DFT2G
  • NL17SZ17DFT2GDFT1G
  • NL17SZ17DFT2GDBVT1G
  • NL17SZ17DFT2GDBVT2G
  • NL17SZ17DFT2GXV5T1G
  • NL17SZ17DFT2GXV5T2G
  • NL17SZ17DFT2GP5T5G

CAD (KiCad official)

  • Symbol: NL17SZ17DFT2G
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: nl17sz17dft2g-etched.step / nl17sz17dft2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nl17sz17dft2g.step / nl17sz17dft2g.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
nl17sz17dft2g.step 87 KB You want the bare part, or you mark your own boards.
nl17sz17dft2g-etched.step 1.8 MB You want the part with NL17SZ17DFT2G already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 462 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (13 pp, sha256 4f064e4b71f6c8b5, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF