component
NL17SV08XV5T2G
Public Made by Adomby adom
onsemi Logic Gates, SOT-553-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NL17SV08XV5T2G
onsemi · Logic Gates · SOT-553-5
NL17SV08XV5T2G from onsemi, in a SOT-553-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN A | input | Gate input A; overvoltage tolerant so it can accept up to 3.6 V (recommended VIN 0 to 3.6 V) for logic translation. |
| 2 | IN B | input | Gate input B; overvoltage tolerant so it can accept up to 3.6 V (recommended VIN 0 to 3.6 V) for logic translation. |
| 3 | GND | power_in | Ground reference for all voltages; maximum ground current is ±50 mA per ground pin. |
| 4 | OUT Y | output | AND gate output (Y = A AND B) with balanced ±24 mA drive at 3.3 V supply. |
| 5 | VCC | power_in | Positive supply, recommended 0.9 to 3.6 V (absolute maximum −0.5 to +4.6 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOT-553-5 |
| Category | Logic |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | 4.6 | V | 2 | ||
| DC Input Voltage | VI | -0.5 | 4.6 | V | 2 | ||
| DC Output Voltage | VO | -0.5 | V | 2 | |||
| DC Input Diode Current | IIK | -50 | mA | VIN < 0 V | 2 | ||
| DC Output Diode Current | IOK | -50 | mA | VOUT < 0 V | 2 | ||
| DC Output Diode Current | IOK | 50 | mA | VOUT > VCC | 2 | ||
| DC Output Sink Current | IO | -50 | 50 | mA | 2 | ||
| DC Supply Current per Supply Pin | ICC | -50 | 50 | mA | 2 | ||
| DC Ground Current per Ground Pin | IGND | -50 | 50 | mA | 2 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Lead Temperature | TL | 260 | °C | 1.0 mm from case for 10 seconds | 2 | ||
| Junction Temperature Under Bias | TJ | 150 | °C | 2 | |||
| Thermal Resistance (Note 1) | JA | 250 | °C/W | Note 1: minimum pad spacing, FR4, 10 mm by 1 inch 2 oz copper trace, no air flow | 2 | ||
| Power Dissipation in Still Air | PD | 250 | mW | at 85°C, still air | 2 | ||
| Positive DC Supply Voltage | VCC | 0.9 | 3.6 | V | 2 | ||
| Digital Input Voltage | VIN | 0 | 3.6 | V | 2 | ||
| Output Voltage | Vout | 0 | V | 2 | |||
| Output Current | IOH/IOL | -24 | 24 | mA | VCC = 3.0 V to 3.6 V | 2 | |
| Output Current | IOH/IOL | -18 | 18 | mA | VCC = 2.3 V to 2.7 V | 2 | |
| Output Current | IOH/IOL | -6 | 6 | mA | VCC = 1.65 V to 1.95 V | 2 | |
| Output Current | IOH/IOL | -4 | 4 | mA | VCC = 1.4 V to 1.6 V | 2 | |
| Output Current | IOH/IOL | -2 | 2 | mA | VCC = 1.1 V to 1.3 V | 2 | |
| Output Current | IOH/IOL | -0.1 | 0.1 | mA | VCC = 0.9 V | 2 | |
| Operating Temperature Range. All Package Types | tA | -40 | 85 | °C | 2 | ||
| Input Rise or Fall Time | tr, tf | 0 | 10 | nS/V | VCC = 3.3 V ± 0.3 V | 2 | |
| Quiescent Supply Current | ICC | 5 | µA | VI = VCC or GND; VCC = 0.90 to 3.60 V; TA = −40 to 85°C | 3 | ||
| Input Leakage Current | IIN | -0.9 | 0.9 | µA | 0 = VI = 3.6 V; VCC = 0.90 to 3.60 V; TA = −40 to 85°C | 3 | |
| Power Off Leakage Current | IOFF | 10 | µA | VCC = 0 V; TA = −40 to 85°C | 3 | ||
| High Level Input Voltage | VIH | 1.6 | V | 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| High Level Input Voltage | VIH | 2 | V | 2.70 ≤ VCC ≤ 3.60; TA = −40 to 85°C | 3 | ||
| Low Level Input Voltage | VIL | 0.7 | V | 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| Low Level Input Voltage | VIL | 0.8 | V | 2.70 ≤ VCC ≤ 3.60; TA = −40 to 85°C | 3 | ||
| High Level Output Voltage | VOH | 1.25 | V | IOH = −6.0 mA; 1.65 ≤ VCC ≤ 1.95; TA = −40 to 85°C | 3 | ||
| High Level Output Voltage | VOH | 2 | V | IOH = −6.0 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| High Level Output Voltage | VOH | 1.8 | V | IOH = −12 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| High Level Output Voltage | VOH | 2.2 | V | IOH = −12 mA; 2.70 < VCC ≤ 3.60; TA = −40 to 85°C | 3 | ||
| High Level Output Voltage | VOH | 1.7 | V | IOH = −18 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| High Level Output Voltage | VOH | 2.4 | V | IOH = −18 mA; 2.70 < VCC ≤ 3.60; TA = −40 to 85°C | 3 | ||
| Low Level Output Voltage | VOL | 0.1 | V | IOL = 100 µA; VCC = 0.90 V; TA = −40 to 85°C | 3 | ||
| Low Level Output Voltage | VOL | 0.2 | V | IOL = 100 µA; 1.40 ≤ VCC ≤ 1.60; TA = −40 to 85°C | 3 | ||
| Low Level Output Voltage | VOL | 0.3 | V | IOL = 6.0 mA; 1.65 ≤ VCC ≤ 1.95; TA = −40 to 85°C | 3 | ||
| Low Level Output Voltage | VOL | 0.4 | V | IOL = 12 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| Low Level Output Voltage | VOL | 0.6 | V | IOL = 18 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 | ||
| Low Level Output Voltage | VOL | 0.55 | V | IOL = 24 mA; 2.70 ≤ VCC ≤ 3.60; TA = −40 to 85°C | 3 | ||
| Input Capacitance | CIN | 2 | pF | VCC = 0 V | 4 | ||
| Output Capacitance | COUT | 4.5 | pF | VCC = 0 V | 4 |
CAD (KiCad official)
- Symbol:
NL17SV08XV5T2G - Footprint:
Package_TO_SOT_SMD:SOT-553 - 3D model: SOT-553-5 (KiCad packages3D, STEP)
- 3D model files:
nl17sv08xv5t2g-etched.step/nl17sv08xv5t2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nl17sv08xv5t2g.step/nl17sv08xv5t2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (5 pp, sha256
e686d0877f9da5f7, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NL17SV08XV5T2G
**onsemi** · Logic Gates · SOT-553-5
NL17SV08XV5T2G from onsemi, in a SOT-553-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN A | input | Gate input A; overvoltage tolerant so it can accept up to 3.6 V (recommended VIN 0 to 3.6 V) for logic translation. |
| 2 | IN B | input | Gate input B; overvoltage tolerant so it can accept up to 3.6 V (recommended VIN 0 to 3.6 V) for logic translation. |
| 3 | GND | power_in | Ground reference for all voltages; maximum ground current is ±50 mA per ground pin. |
| 4 | OUT Y | output | AND gate output (Y = A AND B) with balanced ±24 mA drive at 3.3 V supply. |
| 5 | VCC | power_in | Positive supply, recommended 0.9 to 3.6 V (absolute maximum −0.5 to +4.6 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOT-553-5 |
| Category | Logic |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage | VCC | -0.5 | | 4.6 | V | | 2 |
| DC Input Voltage | VI | -0.5 | | 4.6 | V | | 2 |
| DC Output Voltage | VO | -0.5 | | | V | | 2 |
| DC Input Diode Current | IIK | -50 | | | mA | VIN < 0 V | 2 |
| DC Output Diode Current | IOK | -50 | | | mA | VOUT < 0 V | 2 |
| DC Output Diode Current | IOK | | | 50 | mA | VOUT > VCC | 2 |
| DC Output Sink Current | IO | -50 | | 50 | mA | | 2 |
| DC Supply Current per Supply Pin | ICC | -50 | | 50 | mA | | 2 |
| DC Ground Current per Ground Pin | IGND | -50 | | 50 | mA | | 2 |
| Storage Temperature Range | TSTG | -65 | | 150 | °C | | 2 |
| Lead Temperature | TL | | | 260 | °C | 1.0 mm from case for 10 seconds | 2 |
| Junction Temperature Under Bias | TJ | | | 150 | °C | | 2 |
| Thermal Resistance (Note 1) | JA | | | 250 | °C/W | Note 1: minimum pad spacing, FR4, 10 mm by 1 inch 2 oz copper trace, no air flow | 2 |
| Power Dissipation in Still Air | PD | | | 250 | mW | at 85°C, still air | 2 |
| Positive DC Supply Voltage | VCC | 0.9 | | 3.6 | V | | 2 |
| Digital Input Voltage | VIN | 0 | | 3.6 | V | | 2 |
| Output Voltage | Vout | 0 | | | V | | 2 |
| Output Current | IOH/IOL | -24 | | 24 | mA | VCC = 3.0 V to 3.6 V | 2 |
| Output Current | IOH/IOL | -18 | | 18 | mA | VCC = 2.3 V to 2.7 V | 2 |
| Output Current | IOH/IOL | -6 | | 6 | mA | VCC = 1.65 V to 1.95 V | 2 |
| Output Current | IOH/IOL | -4 | | 4 | mA | VCC = 1.4 V to 1.6 V | 2 |
| Output Current | IOH/IOL | -2 | | 2 | mA | VCC = 1.1 V to 1.3 V | 2 |
| Output Current | IOH/IOL | -0.1 | | 0.1 | mA | VCC = 0.9 V | 2 |
| Operating Temperature Range. All Package Types | tA | -40 | | 85 | °C | | 2 |
| Input Rise or Fall Time | tr, tf | 0 | | 10 | nS/V | VCC = 3.3 V ± 0.3 V | 2 |
| Quiescent Supply Current | ICC | | | 5 | µA | VI = VCC or GND; VCC = 0.90 to 3.60 V; TA = −40 to 85°C | 3 |
| Input Leakage Current | IIN | -0.9 | | 0.9 | µA | 0 = VI = 3.6 V; VCC = 0.90 to 3.60 V; TA = −40 to 85°C | 3 |
| Power Off Leakage Current | IOFF | | | 10 | µA | VCC = 0 V; TA = −40 to 85°C | 3 |
| High Level Input Voltage | VIH | 1.6 | | | V | 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| High Level Input Voltage | VIH | 2 | | | V | 2.70 ≤ VCC ≤ 3.60; TA = −40 to 85°C | 3 |
| Low Level Input Voltage | VIL | | | 0.7 | V | 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| Low Level Input Voltage | VIL | | | 0.8 | V | 2.70 ≤ VCC ≤ 3.60; TA = −40 to 85°C | 3 |
| High Level Output Voltage | VOH | 1.25 | | | V | IOH = −6.0 mA; 1.65 ≤ VCC ≤ 1.95; TA = −40 to 85°C | 3 |
| High Level Output Voltage | VOH | 2 | | | V | IOH = −6.0 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| High Level Output Voltage | VOH | 1.8 | | | V | IOH = −12 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| High Level Output Voltage | VOH | 2.2 | | | V | IOH = −12 mA; 2.70 < VCC ≤ 3.60; TA = −40 to 85°C | 3 |
| High Level Output Voltage | VOH | 1.7 | | | V | IOH = −18 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| High Level Output Voltage | VOH | 2.4 | | | V | IOH = −18 mA; 2.70 < VCC ≤ 3.60; TA = −40 to 85°C | 3 |
| Low Level Output Voltage | VOL | | | 0.1 | V | IOL = 100 µA; VCC = 0.90 V; TA = −40 to 85°C | 3 |
| Low Level Output Voltage | VOL | | | 0.2 | V | IOL = 100 µA; 1.40 ≤ VCC ≤ 1.60; TA = −40 to 85°C | 3 |
| Low Level Output Voltage | VOL | | | 0.3 | V | IOL = 6.0 mA; 1.65 ≤ VCC ≤ 1.95; TA = −40 to 85°C | 3 |
| Low Level Output Voltage | VOL | | | 0.4 | V | IOL = 12 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| Low Level Output Voltage | VOL | | | 0.6 | V | IOL = 18 mA; 2.30 ≤ VCC ≤ 2.70; TA = −40 to 85°C | 3 |
| Low Level Output Voltage | VOL | | | 0.55 | V | IOL = 24 mA; 2.70 ≤ VCC ≤ 3.60; TA = −40 to 85°C | 3 |
| Input Capacitance | CIN | | | 2 | pF | VCC = 0 V | 4 |
| Output Capacitance | COUT | | | 4.5 | pF | VCC = 0 V | 4 |
## CAD (KiCad official)
- Symbol: `NL17SV08XV5T2G`
- Footprint: `Package_TO_SOT_SMD:SOT-553`
- 3D model: SOT-553-5 (KiCad packages3D, STEP)
- 3D model files: `nl17sv08xv5t2g-etched.step` / `nl17sv08xv5t2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nl17sv08xv5t2g.step` / `nl17sv08xv5t2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881774260989952) (5 pp, sha256 `e686d0877f9da5f7`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/nl17sv08xv5t2g-datasheet.pdf)