# NJG1144KA1-TE1

**JRC** · Low Noise Amplifiers (LNA) - RF · SOT-563

NJG1144KA1-TE1 from JRC, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFOUT | output | RF output and voltage supply terminal; supply range is 1.5V to 3.6V (absolute maximum 5.0V). |
| 2 | GND | power_in | Ground terminal (0V), connect to the PCB ground plane. |
| 3 | GND | power_in | Ground terminal (0V), connect to the PCB ground plane. |
| 4 | RFIN | input | RF input terminal; a DC blocking capacitor is not required but an external matching circuit is required. |
| 5 | GND | power_in | Ground terminal (0V), connect to the PCB ground plane. |
| 6 | NC(GND) | passive | Not connected to the internal circuit; the datasheet says to connect it to the PCB ground plane. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | JRC |
| Package | SOT-563 |
| Category | RF And Wireless |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 1.5 |  | 3.6 | V |  | 2 |
| Operating Frequency | freq | 1.57 | 1.575 | 1.58 | GHz |  | 3 |
| Small signal Gain | Gain 1 | 18 | 21 | 23.5 | dB |  | 3 |
| Noise Figure | NF1 |  | 0.65 | 0.95 | dB | Exclude PCB, Connector Losses(0.08dB) | 3 |
| Input Power at 1dB Gain Compression Point 1 | P-1dB(IN)1 | -19 | -16.5 |  | dBm |  | 3 |
| Input 3rd Order Intercept Point 1 | IIP3_1 | -5 | -2 |  | dBm | f1=fRF, f2=f1+100kHz, Pin=-34dBm | 3 |
| RF Input VSWR 1 | VSWRi 1 |  | 1.5 | 2 |  |  | 3 |
| RF Output VSWR 1 | VSWRo1 |  | 1.5 | 2 |  |  | 3 |
| Operating Current 1 (RF table, VDD=2.85V) | IDD 1 |  | 3.5 | 5.5 | mA | RF OFF | 3 |
| Supply Current 1 | IDD 1 |  | 3.5 | 5.5 | mA | RF OFF, VDD=2.85V | 2 |
| Supply Current 2 | IDD 2 |  | 1.8 | 3.2 | mA | RF OFF, VDD=1.8V | 2 |
| Operating Current 2 | IDD 2 |  | 1.8 | 3.2 | mA | RF OFF | 3 |
| Supply voltage (absolute maximum) | VDD |  |  | 5 | V |  | 2 |
| Input power | PIN |  |  | 15 | dBm | VDD =2.85V | 2 |
| Power dissipation | PD |  |  | 580 | mW | 4-layer FR4 PCB with through-hole (74.2mmx74.2mm), Tj=150°C | 2 |
| Operating temperature | Topr | -40 |  | 85 | °C |  | 2 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 2 |

## CAD (KiCad official)

- Symbol: `NJG1144KA1-TE1`
- Footprint: `Package_TO_SOT_SMD:SOT-563`
- 3D model: SOT-563 (KiCad packages3D, STEP)
- 3D model files: `njg1144ka1-te1-etched.step` / `njg1144ka1-te1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `njg1144ka1-te1.step` / `njg1144ka1-te1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [JRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589838391819857920) (15 pp, sha256 `c0f6a926181fd705`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/njg1144ka1-te1-datasheet.pdf)