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NIS5132MN2TXG

Public Made by Adom

by adom

onsemi Surge Suppressors, DFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttvs-fuse-board level protectionnis5132mn2txgfactory-2.0.0extractor-text
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Contents

README

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NIS5132MN2TXG

onsemi · Surge Suppressors · DFN-10(3x3)

NIS5132MN2TXG from onsemi, in a DFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Negative input voltage to the device, used as the internal reference for the IC.
2 dv/dt passive Controls output voltage slew rate at turn-on with an internal capacitor giving about 2 ms ramp; an external capacitor can be added to lengthen the ramp, and the pin is left open if no extra delay is needed.
3 Enable/Fault bidirectional Tri-state bidirectional pin that disables the output when pulled to ground by an open-drain/collector device and goes to an intermediate level (1.4 V typ) on thermal fault; can be tied to other devices in the family for simultaneous shutdown (max fanout 3).
4 ILIMIT passive A resistor between this pin and the source pin sets the overload and short-circuit current limit levels.
5 NC unconnected No connection.
6 SOURCE power_out Source of the internal power FET and the output terminal of the fuse (pins 6-10 are common).
7 SOURCE power_out Source of the internal power FET and the output terminal of the fuse (pins 6-10 are common).
8 SOURCE power_out Source of the internal power FET and the output terminal of the fuse (pins 6-10 are common).
9 SOURCE power_out Source of the internal power FET and the output terminal of the fuse (pins 6-10 are common).
10 SOURCE power_out Source of the internal power FET and the output terminal of the fuse (pins 6-10 are common); one source pin may be used as Kelvin sense connection.
11 VCC power_in Positive input voltage to the device (exposed belly pad/flag), operating range 9 V to 18 V steady-state.

Key specifications

Parameter Value
Manufacturer onsemi
Package DFN-10(3x3)
Category TVS/Fuse/Board Level Protection
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage, operating, steady-state VIN -0.6 18 V VCC to GND 2
Input Voltage, transient VIN -0.6 25 V 100 ms 2
Thermal Resistance, Junction-to-Air RθJA 227 °C/W 0.1 in2 copper 2
Thermal Resistance, Junction-to-Air RθJA 95 °C/W 0.5 in2 copper 2
Thermal Resistance, Junction-to-Lead (Pin 1) RθJL 27 °C/W 2
Thermal Resistance, Junction-to-Case RθJC 20 °C/W 2
Total Power Dissipation Pmax 1.3 W TA = 25°C 2
Power derating above 25°C 10.4 mW/°C Derate above 25°C 2
Operating Temperature Range TJ -40 150 °C 2
Nonoperating Temperature Range TJ -55 155 °C 2
Lead Temperature, Soldering TL 260 °C 10 sec 2
Kelvin ON Resistance RDSon 35 44 55 mΩ VCC = 12 V, Tj = 25°C 3
Kelvin ON Resistance at 140°C RDSon 62 mΩ TJ = 140°C 3
Off State Output Voltage Voff 190 300 mV VCC = 18 Vdc, VGS = 0 Vdc, RL = ∞ 3
Continuous Current ID 3.6 A TA = 25°C, 0.5 in2 pad 3
Continuous Current ID 1.7 A TA = 80°C, minimum copper 3
Shutdown Temperature TSD 150 175 200 °C 3
Output Clamping Voltage VClamp 14 15 16.2 V VCC = 18 V 3
Undervoltage Lockout VUVLO 7.7 8.5 9.3 V Turn on, voltage going high 3
Kelvin Short Circuit Current Limit ILim-SS 2.75 3.44 4.25 A RLimit = 15.4 Ω 3
Output Voltage Ramp Time tslew 0.5 0.9 1.8 ms Enable to VOUT = 11.7 V 3
Logic Level Low Vin-low 0.35 0.58 0.81 V Output Disabled 3
Logic Level Mid Vin-mid 0.82 1.4 1.95 V Thermal Fault, Output Disabled 3
Logic Level High Vin-high 1.96 2.64 3.3 V Output Enabled 3
High State Maximum Voltage Vin-max 3.4 4.3 5.2 V 3
Logic Low Sink Current Iin-low -25 -17 µA Venable = 0 V 3
Logic High Leakage Current Iin-leak 1 µA Venable = 3.3 V 3
Bias Current (Operational) IBias 1.8 2.5 mA 3
Bias Current (Shutdown) IBias 1 mA 3
Minimum Operating Voltage Vmin 7.6 V Verified by design 3
Thermal Hysteresis THyst 45 °C Decrease in die temperature for turn on 3
UVLO Hysteresis VHyst 0.8 V 3
Kelvin Overload Current Limit ILim-OL 4.6 A RLimit = 15.4 Ω 3
Delay Time Tdly 220 µs Enabling of chip to ID = 100 mA with 1 A resistive load 3
Output Capacitance 250 pF VDS = 12 Vdc, VGS = 0 Vdc, f = 1 MHz 3
Maximum Fanout for Fault Signal Fan 3 Units 3
Input Voltage Range 9 18 V 1

CAD (KiCad official)

  • Symbol: NIS5132MN2TXG
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: DFN-10(3x3) (KiCad packages3D, STEP)
  • 3D model files: nis5132mn2txg-etched.step / nis5132mn2txg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nis5132mn2txg.step / nis5132mn2txg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 6c3683b20fc07a59, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF