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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

NE556

GR · Timers / Clock Oscillators · SOP-14

NE556 from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DISCHARGE1	output	Timer 1 discharge pin. Open-collector NPN transistor to GND; used to discharge the external timing capacitor when the internal flip-flop is set. VCE(sat) ~0.15 V @ 15 mA, leakage ~10 nA.
2	THRESHOLD1	input	Timer 1 threshold input. When VTHRES rises above 2/3 VCC the internal comparator resets the flip-flop and drives OUT low. Input current ~250 nA typ.
3	CONTROL1	input	Timer 1 control voltage. Direct access to the 2/3 VCC comparator reference; typically bypassed to GND with 10 nF. VCONT ~10 V typ at VCC=15 V; ~3.3 V typ at VCC=5 V.
4	RESET1	input	Timer 1 active-low reset. When pulled below ~0.7 V the timer output is forced low and the discharge transistor turns on, regardless of TRIG/THRES. Tie to VCC when reset is not used.
5	OUTPUT1	output	Timer 1 push-pull output. Sources or sinks up to 200 mA. VOH ~12.0 V at IOH=-200 mA (VCC=15 V); VOL ~2.7 V at IOL=200 mA. Rise/fall ~100 ns with CL=15 pF.
6	TRIGGER1	input	Timer 1 active-low trigger input. When VTRIG falls below 1/3 VCC the flip-flop is set, driving OUT high and turning off the discharge transistor. Input current ~500 nA typ.
7	GND	power_in	Device ground, shared by both timers. 0 V reference.
8	TRIGGER2	input	Timer 2 active-low trigger input. When VTRIG falls below 1/3 VCC the flip-flop is set, driving OUT high and turning off the discharge transistor. Input current ~500 nA typ.
9	OUTPUT2	output	Timer 2 push-pull output. Sources or sinks up to 200 mA. VOH ~12.0 V at IOH=-200 mA (VCC=15 V); VOL ~2.7 V at IOL=200 mA.
10	RESET2	input	Timer 2 active-low reset. When pulled below ~0.7 V the timer output is forced low and the discharge transistor turns on. Tie to VCC when reset is not used.
11	CONTROL2	input	Timer 2 control voltage. Direct access to the 2/3 VCC comparator reference; typically bypassed to GND with 10 nF.
12	THRESHOLD2	input	Timer 2 threshold input. When VTHRES rises above 2/3 VCC the internal comparator resets the flip-flop and drives OUT low.
13	DISCHARGE2	output	Timer 2 discharge pin. Open-collector NPN transistor to GND; used to discharge the external timing capacitor.
14	VCC	power_in	Positive supply, shared by both timers. Operating range 4.5 V to 16 V; absolute maximum 18 V. ICC ~11 mA typ at VCC=15 V (output high).

Key specifications

Parameter	Value
Manufacturer	GR
Package	SOP-14
Category	RTC
Pins	14

CAD (KiCad official)

Symbol: NE556
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOP-14 (KiCad packages3D, STEP)
3D model files: ne556-etched.step / ne556-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ne556.step / ne556.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: GR datasheet (6 pp, sha256 c3f223235fefd260, retrieved 2026-08-17, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF