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NCV887001D1R2G

Public Made by Adom

by adom

onsemi DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV887001D1R2G

onsemi · DC-DC Converters · SOIC-8

NCV887001D1R2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN/SYNC input Enable and synchronization input whose falling edge synchronizes the internal oscillator, and the part enters sleep mode when this pin is held low longer than the enable time-out period.
2 ISNS input Current sense input, connected to the source of the external N-MOSFET through a current-sense resistor to ground, used for switching-current regulation and current limiting.
3 GND power_in Ground reference for the device.
4 GDRV output Gate driver output that connects to the gate of the external N-MOSFET, with an optional series resistance to tailor EMC performance.
5 VDRV power_out Internally regulated driving-voltage supply for the external N-MOSFET, sourced from VIN, to be bypassed with a 1.0 F ceramic capacitor to ground (as printed in the datasheet).
6 VIN power_in Input voltage pin for the device, rated 3.2 V to 40 V operating with 45 V load dump, and absolute maximum DC supply of -0.3 V to 40 V; a diode from the input supply to VIN is needed for bootstrapping.
7 VC output Output of the voltage error amplifier, with an external compensator network from VC to GND used to stabilize the converter; absolute maximum DC voltage is -0.3 V to 3.6 V.
8 VFB input Output voltage feedback input, where a resistor divider from the output to VFB and VFB to GND sets the regulated output voltage; absolute maximum DC voltage is -0.3 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (VIN) -0.3 40 V 2
Peak Transient Voltage (Load Dump on VIN) 45 V Load Dump on VIN 2
DC Supply Voltage (VDRV, GDRV) 12 V 2
Peak Transient Voltage (VFB) -0.3 6 V 2
DC Voltage (VC, VFB, ISNS) -0.3 3.6 V 2
DC Voltage (EN/SYNC) -0.3 6 V 2
DC Voltage Stress (VIN − VDRV) -0.7 40 V 2
Operating Junction Temperature -40 150 °C 2
Storage Temperature Range -65 150 °C 2
Peak Reflow Soldering Temperature 265 °C Pb-Free, 60 to 150 seconds at 217°C 2
Quiescent Current, Sleep Mode (−40°C<TJ<125°C) Iq,sleep 2 6 A VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C 3
Quiescent Current, No switching Iq,off 1.5 2.5 mA Into VIN pin, EN = 1, No Switching 3
Quiescent Current, Switching, Normal Operation Iq,on 3 6 mA Into VIN pin, EN = 1, Switching 3
Minimum Pulse Width ton,min 200 250 300 ns 3
Maximum Duty Cycle Dmax 91 93 95 % NCV887001 3
Switching Frequency fs 90 100 110 kHz NCV887001 3
Soft-Start Time tss 10.5 13 15.5 ms From start of switching with VFB = 0 until reference voltage = VREF; NCV887001 3
Soft-Start Delay tss,dly 720 840 s From EN → 1 until start of switching with VFB = 0 3
Slope Compensating Ramp Sa 28 33 38 mV/s NCV887001 3
EN/SYNC Pull-down Current IEN/SYNC 5 10 A VEN/SYNC = 5 V 4
EN/SYNC Input High Voltage Vs,ih 2 5 V VIN > VUVLO 4
EN/SYNC Input Low Voltage Vs,il 0 800 mV 4
EN/SYNC Time-out Ratio %ten 350 % From SYNC falling edge, to oscillator control (EN high) or shutdown (EN low), Percent of typical switching period 4
SYNC Minimum Frequency Ratio %fsync,min 80 % Percent of fs 4
SYNC Maximum Frequency fsync,max 1.1 MHz 4
Synchronization Delay ts,dly 50 100 ns From SYNC falling edge to GDRV falling edge under open loop conditions 4
Synchronization Duty Cycle Dsync 25 75 % 4
Low-frequency Gain Acsa 0.9 1 1.1 V/V Input-to-output gain at dc, ISNS ≤ 1 V 4
Bandwidth BWcsa 2.5 MHz Gain of Acsa −3 dB 4
ISNS Input Bias Current Isns,bias 30 50 A Out of ISNS pin 4
Current Limit Threshold Voltage Vcl 360 400 440 mV Voltage on ISNS pin; NCV887001 4
Current Limit, Response Time tcl 80 125 ns CL tripped until GDRV falling edge, VISNS = Vcl(typ) + 60 mV 4
Overcurrent Protection, Threshold Voltage %Vocp 125 150 175 % Percent of Vcl 4
Overcurrent Protection, Response Time tocp 80 125 ns From overcurrent event, Until switching stops, VISNS = VOCP + 40 mV 4
Transconductance gm,vea 0.8 1.2 1.63 mS VFB, Vref = ±20 mV 4
VEA Output Resistance Ro,vea 2 M 4
VFB Input Bias Current Ivfb,bias 0.5 2 A Current out of VFB pin 4
Reference Voltage Vref 1.176 1.2 1.224 V 4
VEA Maximum Output Voltage Vc,max 2.5 V 4
VEA Minimum Output Voltage Vc,min 0.3 V 4
VEA Sourcing Current Isrc,vea 80 100 A VEA output current, Vc = 2.0 V 4
VEA Sinking Current Isnk,vea 80 100 A VEA output current, Vc = 0.7 V 4
Gate Driver Sourcing Current Isrc 600 800 mA VDRV ≥ 6 V, VDRV − VGDRV = 2 V; NCV887001 4
Gate Driver Sinking Current Isink 500 600 mA VGDRV ≥ 2 V; NCV887001 4
Driving Voltage Dropout Vdrv,do 0.2 0.35 V VIN − VDRV, IVDRV = 10 mA 4
Driving Voltage Source Current Idrv 10 15 mA VIN − VDRV = 1 V 4
Backdrive Diode Voltage Drop Vd,bd 0.7 V VDRV − VIN, Id,bd = 5 mA 4
Driving Voltage VDRV 10 10.5 11 V IVDRV = 0.1 − 25 mA; NCV887001 4
Undervoltage Lock-out Threshold Voltage Vuvlo 3 3.1 3.2 V VIN falling 5
Undervoltage Lock-out Hysteresis Vuvlo,hys 50 125 200 mV VIN rising 5
Startup Blanking Period %tscp,dly 100 120 150 % From start of soft-start, Percent of tss 5
Hiccup-mode Period %thcp,dly 65 80 95 % From shutdown to start of soft-start, Percent of tss 5
Short Circuit Threshold Voltage %Vscp 60 67 75 % VFB as percent of Vref 5
Short Circuit Delay tscp 35 100 ns From VFB < Vscp to stop switching 5
Thermal Shutdown Threshold Tsd 160 170 180 °C TJ rising 5
Thermal Shutdown Hysteresis Tsd,hys 10 15 20 °C TJ falling 5
Thermal Shutdown Delay tsd,dly 100 ns From TJ > Tsd to stop switching 5
Package Thermal Resistance Junction-to-Ambient RθJA 100 °C/W 1 in2, 1 oz copper area used for heatsinking 3

CAD (KiCad official)

  • Symbol: NCV887001D1R2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv887001d1r2g-etched.step / ncv887001d1r2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv887001d1r2g.step / ncv887001d1r2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (17 pp, sha256 1f3c3c6e3bb0722b, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF