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NCV8518CPDR2G

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onsemi Linear Voltage Regulators (LDO), SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV8518CPDR2G

onsemi · Linear Voltage Regulators (LDO) · SOIC-8-EP

NCV8518CPDR2G from onsemi, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Wake Up output Continuously generated signal that interrupts the microprocessor from sleep mode, 50% nominal duty cycle, output high 4.86 V typ, pulled low during RESET.
2 GND power_in Power supply ground.
3 Delay passive Delay timing pin: buffered reference voltage (0.48 V typ) used to create timing current for RESET and watchdog threshold frequency from RDelay to ground.
4 VOUT power_out Regulated 5.0 V output (±2%) with up to 250 mA output capability; requires at least 1.0 µF output capacitor.
5 VIN power_in Positive power supply, 6.0 V to 28 V recommended (45 V peak transient); connect capacitor to ground.
6 ENABLE input Enable input: low level (≤0.8 V) disables the chip, high level (≥2.0 V) enables it; connect to VIN if this function is not needed.
7 WDI input CMOS compatible watchdog input that monitors the falling edge of the incoming signal; absolute maximum is 7.0 V.
8 RESET output CMOS compatible reset output that goes low when VOUT drops more than 7.0% from nominal or when no correct watchdog signal is present.
9 EPAD passive Exposed pad; connect to ground potential or leave unconnected.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8-EP
Category Power Supply Chip
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage VOUT 4.9 5 5.1 V 6.0 V ≤ VIN ≤ 28 V, 100 µA ≤ IOUT ≤ 150 mA 6
Dropout Voltage VDO 356 750 mV IOUT = 150 mA 6
Load Regulation Regload -30 30 mV VIN = 13.5 V, IOUT = 100 µA to 150 mA 6
Line Regulation Regline -20 20 mV IOUT = 5.0 mA, VIN = 6.0 V to 28 V 6
Current Limit ILIM 255 510 mA VOUT = 0.95 x VOUT_nom, Vin = 13.5 V 6
Thermal Shutdown TJmax 150 175 210 °C Guaranteed by design 6
Quiescent Current Iq 70 85 µA VIN = 13.5 V, IOUT = 100 µA, VENABLE = 2.0 V 6
Disable Current IDIS 1 µA VENABLE = 0 V, TA ≤ +125°C 6
RESET Threshold Voltage 4.5 4.65 4.75 V 6
RESET Output Low 0.025 0.4 V RRESET = 10 kΩ to VOUT, VOUT = 1.0 V 6
RESET Output High 4.5 4.86 V RRESET = 10 kΩ to GND 6
Power On Reset Delay Time POR 2 3.1 4 ms VIN = 13.5 V, RDelay = 60 kΩ, IOUT = 5.0 mA 6
Watchdog Threshold Voltage WDIhigh 30 50 70 % of VOUT 6
Watchdog Hysteresis WDIhys 25 100 mV Guaranteed by design 6
Watchdog Input Current 1.1 2 µA WDI = 6.0 V 6
ENABLE Threshold Logic Low Vth(ENABLE) 0.8 V VOUT ≤ 0.1 V 6
ENABLE Threshold Logic High Vth(ENABLE) 2 V VOUT ≥ 4.5 V 6
ENABLE Input Current IENABLE 2.4 10 µA VENABLE = 2.0 V 6
Wake Up Period 18 24 32 ms VIN = 13.5 V, IOUT = 5.0 mA, RDelay = 120 kΩ 7
Wake Up Duty Cycle 45 50 55 % Nominal 7
RESET HIGH to Wake Up Rising Delay Time 9 12 16 ms RDelay = 120 kΩ, 50% RESET Rising Edge to 50% Wake Up Edge 7
Wake Up Response to Watchdog Input 0.65 2 µs 50% WDI Falling Edge to 50% Wake Up Falling Edge 7
Wake Up Response to RESET 0.012 1 µs VOUT = 5.0 V→ 4.5 V 7
Wake Up Output Low 0.085 0.4 V RWakeUp = 10 kΩ to VOUT 7
Wake Up Output High 4.5 4.86 V RWakeUp = 10 kΩ to GND 7
DC Input Voltage / ENABLE Voltage VIN, VENABLE -0.3 40 V DC voltage 4
Peak Transient Voltage (Load Dump) VIN, VENABLE 45 V Load Dump Test B, ISO16750-2 4
Output Voltage VOUT -0.3 7 V 4
RESET Output Voltage VRESET -0.3 7 V Pin to Ground only, all other pins left disconnected 4
Wake Up Voltage VWake_Up -0.3 7 V Pin to Ground only, all other pins left disconnected 4
Watchdog Input Voltage VWDI -0.3 7 V 4
Delay Timing Voltage VDelay -0.3 3.6 V 4
Operating Junction Temperature TJ -40 150 °C 4
Storage Temperature Range TS -55 150 °C 4
ESD Capability, Human Body Model ESDHBM -2 2 kV 4
ESD Capability, Charged Device Model ESDCDM -1 1 kV 4
Lead Temperature Soldering: Reflow (Lead-Free) TSLD 265 °C 60-150 sec above 217 °C, 40 sec max at peak 4
Input Voltage VIN 6 28 V 5
Output Current IOUT 0.1 150 mA 5
Junction Temperature TJ -40 150 °C 5
Input Capacitor CIN 0.1 µF Including de-ratings 5
Output Capacitor COUT 1 µF Including de-ratings 5
Power On Reset Delay Time (RDelay 120 kΩ) POR 6.2 ms VIN = 13.5 V, RDelay = 120 kΩ, IOUT = 5.0 mA 6
Reset Reaction Time tRR 20 µs 6
Thermal Resistance Junction to Ambient, SOIC-8 EP RθJA 132.3 °C/W 100 sq. mm spreader board 5
Thermal Resistance Junction to Ambient, SOIC-8 EP RθJA 85.3 °C/W 1 sq. inch spreader board 5
Thermal Resistance Junction to Board, SOIC-8 EP ΨJB 7 °C/W 100 sq. mm spreader board 5
Thermal Resistance Junction to Board, SOIC-8 EP ΨJB 7.5 °C/W 1 sq. inch spreader board 5

CAD (KiCad official)

  • Symbol: NCV8518CPDR2G
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: ncv8518cpdr2g-etched.step / ncv8518cpdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv8518cpdr2g.step / ncv8518cpdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (16 pp, sha256 d738636e5a302f65, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF