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Ray Publish 0.1.0 c555947 15d ago

NCV8164CSNADJT1G

onsemi · Linear Voltage Regulators (LDO) · TSOP-5

NCV8164CSNADJT1G from onsemi, in a TSOP-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage supply pin, operating range 1.6 V to 5.0 V, bypassed with at least a 1 µF ceramic capacitor to GND.
2 GND power_in Common ground connection.
3 EN input Chip enable: VEN < 0.2 V disables the regulator and VEN > 0.7 V enables the LDO.
4 ADJ input Adjustable output feedback pin (adjustable version only), with a 1.2 V reference voltage.
5 OUT power_out Regulated output voltage, to be bypassed with a small 1 µF ceramic capacitor.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSOP-5
Category Power Management ICs
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating Input Voltage VIN 1.6 5 V 4
Output Voltage Accuracy VOUT -2 2 % VIN = VOUT(NOM) + 0.5 V to 5.0 V, 0.1 mA ≤ IOUT ≤ 300 mA 4
Reference Voltage (Adjustable Ver., ADJ pin connected to OUT) VADJ 1.176 1.2 1.224 V VIN = 1.6 V to 5.0 V, 0.1 mA ≤ IOUT ≤ 300 mA 4
Output Current Limit ICL 350 560 mA VOUT = 90% VOUT(NOM) 4
Quiescent Current IQ 30 40 µA IOUT = 0 mA 4
Shutdown Current IDIS 0.01 1.5 µA VEN ≤ 0.4 V 4
EN Pull Down Current IEN 0.2 0.6 µA VEN = 5.0 V 4
EN Input Voltage H VENH 0.7 V 4
EN Input Voltage L VENL 0.2 V 4
Power Good Output Voltage Low VPGLO 0.3 V IPG = 5 mA, Open drain 4
Line Regulation LineReg 0.5 mV/V VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.0 V 4
Load Regulation LoadReg 2 mV IOUT = 1 mA to 300 mA 4
Short Circuit Current ISC 580 mA VOUT = 0 V 4
Power Good Threshold, Output Voltage Raising VPGUP 95 % Output Voltage Raising 4
Power Good Threshold, Output Voltage Falling VPGDW 90 % Output Voltage Falling 4
Turn-On Time 120 µs COUT = 1 µF, From assertion of VEN to VOUT = 95% VOUT(NOM) 4
Thermal Shutdown Threshold TSDH 165 °C Temperature rising 4
Thermal Shutdown Hysteresis THYST 15 °C Temperature hysteresis 4
Input Voltage VIN -0.3 5.3 V 2
Output Voltage VOUT -0.3 5.3 V -0.3 to VIN+0.3, max. 5.3 V 2
Chip Enable Input VCE -0.3 5.3 V 2
Power Good Voltage VPG -0.3 5.3 V 2
Power Good Current IPG 30 mA 2
Maximum Junction Temperature TJ 150 °C 2
Storage Temperature TSTG -55 150 °C 2
ESD Capability, Human Body Model ESDHBM 2000 V 2
ESD Capability, Charged Device Model ESDCDM 1000 V 2
Thermal Resistance, Junction-to-Ambient, TSOP-5 RθJA 158 °C/W TSOP-5 package 3
Thermal Resistance, Junction-to-Case (top), TSOP-5 RθJC(top) 155 °C/W TSOP-5 package 3
Thermal Resistance, Junction-to-Case (bottom), TSOP-5 RθJC(bot) 102 °C/W TSOP-5 package 3
Thermal Resistance, Junction-to-Board, TSOP-5 RθJB 197 °C/W TSOP-5 package 3

CAD (KiCad official)

  • Symbol: NCV8164CSNADJT1G
  • Footprint: Package_SO:TSOP-5_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-5 (KiCad packages3D, STEP)
  • 3D model files: ncv8164csnadjt1g-etched.step / ncv8164csnadjt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv8164csnadjt1g.step / ncv8164csnadjt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 aa35ab4ba7595f41, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF