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Contents

README

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NCV78L08ABDR2G

onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

NCV78L08ABDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Regulated 8.0 V output delivering up to 100 mA; the output capacitor is optional and only improves transient response.
2 GND power_in Ground, electrically common to the die attach flag to lower thermal resistance.
3 GND power_in Ground, electrically common to the die attach flag to lower thermal resistance.
4 NC unconnected No internal connection.
5 NC unconnected No internal connection.
6 GND power_in Ground, electrically common to the die attach flag to lower thermal resistance.
7 GND power_in Ground, electrically common to the die attach flag to lower thermal resistance.
8 VIN power_in Input supply, which must stay typically 2.0 V above the output even at the low point of the input ripple, with an absolute maximum of 30 Vdc for 5.0-9.0 V versions.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage (TJ = +25°C) VO 7.7 8 8.3 Vdc TJ = +25°C, VI = 14 V, IO = 40 mA 3
Output Voltage (over line and load) VO 7.6 8.4 Vdc 10.5 Vdc ≤ VI ≤ 23 Vdc, 1.0 mA ≤ IO ≤ 40 mA 3
Output Voltage (over load) VO 7.6 8.4 Vdc VI = 14 V, 1.0 mA ≤ IO ≤ 70 mA 3
Line Regulation Regline 175 mV TJ = +25°C, IO = 40 mA, 10.5 Vdc ≤ VI ≤ 23 Vdc 3
Line Regulation Regline 125 mV TJ = +25°C, IO = 40 mA, 11 Vdc ≤ VI ≤ 23 Vdc 3
Load Regulation Regload 80 mV TJ = +25°C, 1.0 mA ≤ IO ≤ 100 mA 3
Load Regulation Regload 40 mV TJ = +25°C, 1.0 mA ≤ IO ≤ 40 mA 3
Input Bias Current (TJ = +25°C) IIB 3 6 mA TJ = +25°C 3
Input Bias Current (TJ = +125°C) IIB 5.5 mA TJ = +125°C 3
Input Bias Current Change IIB 1.5 mA 11 Vdc ≤ VI ≤ 23 Vdc 3
Input Bias Current Change IIB 0.1 mA 1.0 mA ≤ IO ≤ 40 mA 3
Ripple Rejection RR 37 57 dB IO = 40 mA, f = 120 Hz, 12 V ≤ VI ≤ 23 V, TJ = +25°C 3
Input Voltage (output 5.0 V to 9.0 V row, applies to 8.0 V device) VI 30 Vdc Input Voltage (5.0 V−9.0 V) row 2
Storage Temperature Range Tstg -65 150 °C 2
Maximum Junction Temperature TJ 150 °C 2
ESD Capability, Human Body Model ESDHBM 2000 V Note 1 2
ESD Capability, Machine Model ESDMM 200 V Note 1 2
ESD Capability, Charged Device Model ESDCDM 2000 V Note 1 2
Operating Junction Temperature Range TJ -40 125 °C MC78LXXAB grade (ordering table: TJ = −40° to +125°C) 10

CAD (KiCad official)

  • Symbol: NCV78L08ABDR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv78l08abdr2g-etched.step / ncv78l08abdr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv78l08abdr2g.step / ncv78l08abdr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (19 pp, sha256 991fda5cdeb9eedc, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF