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NCV7535DBR2G

Public Made by Adom

by adom

onsemi Brushed DC Motor Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV7535DBR2G

onsemi · Brushed DC Motor Drivers · TSSOP-20

NCV7535DBR2G from onsemi, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP output Charge pump output for the high-side gate drive supply.
2 CPM output Minus terminal for the pump capacitor.
3 CPP output Plus terminal for the pump capacitor.
4 VCC power_in Logic supply of the device; recommended operating range 4.5 V to 5.25 V.
5 CSN input SPI chip select input with internal pull-up.
6 SCLK input SPI clock input with internal pull-down.
7 SDI input SPI data input with internal pull-down.
8 SDO tri_state Digital push-pull SPI data output with tristate capability.
9 EN input Enable input with internal pull-down.
10 PWM input Input for the pulse width modulated driver duty cycle, with internal pull-down.
11 GL2 output Output to the gate of low-side switch 2.
12 SH2 bidirectional Connection to the source of high-side switch 2.
13 GH2 output Output to the gate of high-side switch 2.
14 VH input Connection to the drain of the high-side switch for short-circuit detection.
15 GL1 output Output to the gate of low-side switch 1.
16 SH1 bidirectional Connection to the source of high-side switch 1.
17 GH1 output Output to the gate of high-side switch 1.
18 GND power_in Ground connection.
19 CPR output Reverse polarity N-FET control output with a current capability of 1 mA.
20 VS power_in Power supply of the device; parametric operating range 6 V to 18 V, functional range 5 V to 28 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSSOP-20
Category Motor Driver ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage Vmax_VS -0.3 40 V 3
Reverse Polarity FET Control Output Voltage Vmax_CPR -25 40 V 3
Positive Charge-pump CP and CPP voltages Vmax_CP, CPP -0.3 40 V 3
Negative Charge-pump voltage Vmax_CPM -0.3 V 3
Gate driver voltage transient Vmax_GHx, SHx -4 40 V transient < 500 ns 3
Gate driver voltage DC Vmax_GHx, SHx -2 V DC 3
Voltage difference V(GHx) - V(SHx) (high side Vgs) Vmax_VGSx -0.3 17 V Qgate = 60 nC 3
GLx pin voltage transient (low side Vgs) Vmax_GLx -0.3 17 V transient < 500 ns 3
Sense line for VS Vmax_VH -0.3 40 V 3
Logic supply Vmax_VCC 0.3 5.5 V 3
DC voltage at digital pins Vmax_digIO -0.3 V SDI, SDO, SCLK, PWM 3
DC voltage at digital pins Vmax_digIO -0.3 5.8 V CSN, EN 3
Power supply voltage for valid parameter specifications Vop_VS_par 6 18 V 4
Power supply for correct functional behavior Vop_VS_func, VH 5 28 V Note 2 4
Voltage difference GHx - SHx (Vgs) Vop_VGSx 0 17 V Qgate = 60 nC 4
GLx pin voltage range DC Vop_GLx 0 17 V DC, Qgate = 60 nC (voltage internally limited during flyback) 4
Logic supply Vop_VCC 4.5 5.25 V 4
DC voltage at digital pins (SDI, SDO, SCLK, CSN, PWM, EN) Vop_digIO 0 V 4
Junction temperature Tj_op -40 150 °C 4
VS Supply Voltage (functional) VS 5 28 V Functional (see Note 3) 4
VS Supply Voltage (parameter specification) VS 6 18 V Parameter specification 4
VS consumption in Standby mode I_VS_Standby 10 20 A Standby, VS = 12 V, VCC = 0 V or EN = 0, charge pump off; no SPI, Tj = 85°C 4
Vcc consumption in Standby mode I_Vcc_Standby 10 20 A Standby, VS = 12 V, VCC = 5 V, EN = 0, charge pump off; no SPI, Tj = 85°C 4
VS consumption in Active mode I_VS_Active 4 10 mA Active, VS = 12 V, VCC = 5 V, external H-bridge static, no SPI, fPWM = 25 kHz, Qg = 60 nC 4
Vcc consumption in Active mode I_Vcc_Active 3.3 8 mA Active mode 4
VS Under-Voltage detection Vuv_vs(on) 5.6 6.4 V VS increasing 4
VS Under-Voltage detection Vuv_vs(off) 5 5.7 V VS decreasing 4
VS Over-Voltage detection Vov_vs(off) 22.5 24 25.5 V VS increasing 5
VS Over-Voltage detection Vov_vs(on) 20.5 22 23.5 V VS decreasing 5
VCC Under-Voltage detection Vuv_vcc(off) 3 3.2 V VCC increasing 5
VCC Under-Voltage detection Vuv_vcc(on) 2.6 2.8 V VCC decreasing 5
VS Under-Voltage / Over-Voltage filter time td_uvov 48 76 125 s Time to set the power supply fail bit UOV_OC in the Global Status Byte 5
Charge pump frequency fCP 300 425 550 kHz 5
Switch impedance between CPR and CP R_CPR 250 300 420 tested at 0.5 mA 5
Current capability of Reverse Polarity Gate Control I_CPR 1 mA 5
Propagation delay of PWM rising or falling edge to gate activation tprop 200 500 800 ns Measured with dVGxfast & 5 nF load 5
Jitter versus PWM rising or falling edge to gate activations tjitter -150 0 150 ns Measured with dVGxfast & 5 nF load 5
Additional cross conduction protection time, low-to-high transition tdLH -33 33 % Programmable via SPI bits CONFIG.NOCRLH[3:0] 6
Additional cross conduction protection time, high-to-low transition tdHL -33 33 % Programmable via SPI bits CONFIG.NOCRHL[3:0] 6
Programmable Over-Current detection threshold (relative tolerance) Vthoc -10 10 % Programmable via SPI bits CONFIG.OCTH[2:0] 6
Programmable Over-Current detection threshold (absolute tolerance) Vthoc -0.03 0.03 V Programmable via SPI bits CONFIG.OCTH[2:0] 6
Filter time for OC protection t_oc 4 6 12 s 6
Input low level Vinl 30 % VCC VCC = 5 V 6
Input high level Vinh 70 % VCC VCC = 5 V 6
CSN pull-up resistor Rcsn_pu 30 120 250 k VCC = 5 V, 0 V < Vcsn < 70% VCC 7
SCLK pull-down resistor Rsclk_pd 30 60 220 k VCC = 5 V, Vsclk = 1.5 V 7
SDI pull-down resistor Rsdi_pd 30 60 220 k VCC = 5 V, Vsdi = 1.5 V 7
PWM pull-down resistor Rpwm_pd 30 60 220 k VCC = 5 V, Vpwm = 1.5 V 7
EN pull-down resistor Ren_pd 30 120 250 k VCC = 5 V, Ven = 1.5 V 7
Output low level (SDO) Vsdol 20 % VCC Isdo = 5 mA 7
Output high level (SDO) Vsdoh 80 % VCC Isdo = -5 mA 7
Tristate leakage current (SDO) Ileak_sdo -10 10 A Vcsn = VCC, 0 V < Vsdo < VCC 7
Clock period tsclk 1000 ns VCC = 5 V 7
CSN setup time, CSN low before rising edge of SCLK tset_csn 400 ns 7
SCLK setup time, SCLK low before rising edge of CSN tset_sclk 400 ns 7
SDI setup time tset_si 200 ns 7
SDI hold time thold_si 200 ns 7
Thermal shutdown threshold, Tj increasing Tjsd_on 160 175 195 °C Junction temperature 8
Thermal Resistance, Junction-to-Lead RJL 60 °C/W 4
Thermal Reference, Junction-to-Ambient RJA 130 °C/W Typical still air, 1 oz Cu FR4 4-layer PCB, 650 mm2 Cu area (Note 1) 4

CAD (KiCad official)

  • Symbol: NCV7535DBR2G
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ncv7535dbr2g-etched.step / ncv7535dbr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv7535dbr2g.step / ncv7535dbr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (19 pp, sha256 54aeb8416f6d0de6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF