component
NCV7357D13R2G
Public Made by Adomby adom
onsemi CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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NCV7357D13R2G
onsemi · CAN Transceivers · SOIC-8
NCV7357D13R2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TxD | input | Transmit data input; a low level drives the bus dominant, VIL is 0.8 V max and VIH is 2.0 V min, and an internal pull-up current biases the pin when it is disconnected. |
| 2 | GND | power_in | Ground reference; all datasheet voltages are referenced to this pin. |
| 3 | VCC | power_in | Supply voltage, 4.75 V to 5.25 V in the recommended range, with an absolute maximum of 6.0 V. |
| 4 | RxD | output | Receive data output that follows the bus state, with a low output when the transmitter is dominant; IOH is -1.0 to -8.0 mA and IOL is 1.0 to 12 mA. |
| 5 | VIO | power_in | Digital input/output supply pin that should be connected to the microcontroller supply to set I/O levels; 2.8 V to 5.5 V, available on the NCV7357-3 version only. |
| 6 | CANL | bidirectional | Low-level CAN bus line that is driven low in dominant mode, with DC bus pin voltages limited to -42 V to +42 V and protected against automotive transients and short circuits. |
| 7 | CANH | bidirectional | High-level CAN bus line that is driven high in dominant mode, with DC bus pin voltages limited to -42 V to +42 V and protected against automotive transients and short circuits. |
| 8 | S | input | Silent mode control input where a low selects normal mode and a high selects silent mode, with an internal pull-up current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VCC | 4.75 | 5 | 5.25 | V | 7 | |
| Supply current in Normal mode | ICC | 30 | 45 | 55 | mA | Dominant; VTxD = Low | 7 |
| Supply current in Normal mode | ICC | 2 | 5 | 10 | mA | Recessive; VTxD = High | 7 |
| Supply current in Normal mode, one bus wire shorted | ICC | 2 | 105 | mA | Normal mode, Dominant; VTxD = 0 V; one of bus wires shorted; −3 V ≤ (VCANH, VCANL) ≤ +18 V | 7 | |
| Supply current in silent mode (NCV7357-3 version) | ICCS | 0.1 | 1.3 | mA | NCV7357-3 version | 7 | |
| Undervoltage detection on VCC pin | VUVDVCC | 3.5 | 4 | 4.3 | V | 7 | |
| Supply voltage on pin VIO | VIO | 2.8 | 5.5 | V | Only for NCV7357-3 version | 7 | |
| Supply current on pin VIO in silent mode | IIOS | 120 | 200 | µA | VTxD = VIO | 7 | |
| Supply current on pin VIO during normal mode | IIONM | 700 | 900 | µA | Dominant; VTxD = Low | 7 | |
| Supply current on pin VIO during normal mode | IIONM | 460 | 600 | µA | Recessive; VTxD = High | 7 | |
| Undervoltage detection voltage on VIO pin | VUVDVIO | 2 | 2.3 | 2.6 | V | 7 | |
| High-level input voltage (TxD) | VIH | 2 | V | Output recessive | 7 | ||
| Low-level input voltage (TxD) | VIL | -0.3 | 0.8 | V | Output dominant | 7 | |
| Low-level input current (TxD) | IIL | -300 | -150 | -75 | µA | VTxD = 0 V | 7 |
| High-level input voltage (S) | VIH | 2 | V | Silent mode | 7 | ||
| Low-level input voltage (S) | VIL | -0.3 | 0.8 | V | Normal mode | 7 | |
| Low-level input current (S) | IIL | -15 | -1 | µA | VS = 0 V | 7 | |
| High-level output current (RxD) | IOH | -8 | -3 | -1 | mA | Normal mode; VRxD = VCC / VIO, 0.4 V | 8 |
| Low-level output current (RxD) | IOL | 1 | 6 | 12 | mA | VRxD = 0.4 V | 8 |
| Dominant output voltage at pin CANH | Vo(dom)(CANH) | 2.75 | 3.5 | 4.5 | V | Normal mode; VTxD = Low; t < tdom(TxD); 50 < RLT < 65 | 8 |
| Dominant output voltage at pin CANL | Vo(dom)(CANL) | 0.5 | 1.5 | 2.25 | V | Normal mode; VTxD = Low; t < tdom(TxD); 50 < RLT < 65 | 8 |
| Recessive output voltage at pins CANH and CANL | Vo(rec) | 2 | 2.5 | 3 | V | Normal or Silent mode; VTxD = High or VTxD = Low and t > tdom(TxD); no load | 8 |
| Differential dominant output voltage (VCANH − VCANL) | Vo(dom)(diff) | 1.5 | 2.25 | 3 | V | Normal mode; VTxD = Low; t < tdom(TxD); 45 < RLT < 65 | 8 |
| Differential dominant output voltage (arbitration) | Vo(dom)(diff)_ARB | 1.5 | 5 | V | Normal mode; VTxD = Low; t < tdom(TxD); RLT = 2 240 | 8 | |
| Differential recessive output voltage (VCANH − VCANL) | Vo(rec)(diff) | -50 | 0 | 50 | mV | Normal or Silent mode; VTxD = High or VTxD = Low and t > tdom(TxD); no load | 8 |
| Dominant output voltage driver symmetry | Vo(dom)(sym) | 0.9 | 1 | 1.1 | VCC | TxD = square wave up to 1 MHz; CST = 4.7 nF | 8 |
| Short circuit output current at pin CANH in dominant | Io(sc)(CANH) | -100 | -70 | 1 | mA | Normal mode; TxD = Low, t < tdom(TxD); −3 V ≤ VCANH ≤ +18 V | 8 |
| Short circuit output current at pin CANL in dominant | Io(sc)(CANL) | -1 | 70 | 100 | mA | Normal mode; TxD = Low, t < tdom(TxD); −3 V ≤ VCANL ≤ +36 V | 8 |
| Short circuit output current at pins CANH and CANL in recessive | Io(sc)(rec) | -5 | 5 | mA | Normal or Silent mode; TxD = High, −27 V < VCANH, VCANL < + 32 V | 8 | |
| Input leakage current | ILEAK(off) | -5 | 0 | 5 | µA | 0 < R(VCC to GND) < 1 M; VCANH = VCANL = 5 V | 8 |
| Differential input voltage range recessive state | Vi(rec)(diff)_NM | -3 | 0.5 | V | Normal or Silent mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load | 8 | |
| Differential input voltage range dominant state | Vi(dom)(diff)_NM | 0.9 | 8 | V | Normal or Silent mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load | 8 | |
| Differential receiver threshold voltage | Vi(th)(diff)_NM | 0.5 | 0.9 | V | Normal or Silent mode; −12 V ≤ VCANH, VCANL ≤ +12 V; no load | 8 | |
| Differential receiver threshold voltage (extended) | Vi(th)(diff)_NM_E | 0.4 | 1 | V | Normal or Silent mode; extended, −30 V ≤ VCANH, VCANL ≤ +35 V; no load | 8 | |
| Differential input resistance | Ri(diff) | 25 | 50 | 75 | kΩ | −2 V ≤ VCANH, VCANL ≤ +7 V | 9 |
| Propagation delay TxD to RxD dominant to recessive transition | tpd_dr | 50 | 100 | 210 | ns | Normal mode (Note 14) | 9 |
| Propagation delay TxD to RxD recessive to dominant transition | tpd_rd | 50 | 120 | 210 | ns | Normal mode (Note 14) | 9 |
| Operating mode change delay | td(s-nm) | 5 | 11 | 50 | µs | Silent mode to Normal mode | 9 |
| TxD dominant timeout | tdom(TxD) | 1 | 10 | ms | Normal mode; VTxD = Low | 9 | |
| Bit time on RxD pin | tbit(RxD) | 400 | 550 | ns | tbit(TxD) = 500 ns (Note 14) | 9 | |
| Bit time on RxD pin | tbit(RxD) | 120 | 220 | ns | tbit(TxD) = 200 ns (Note 14) | 9 | |
| Bit time on bus (CANH − CANL pin) | tbit(Vi(diff)) | 435 | 530 | ns | tbit(TxD) = 500 ns (Note 14) | 9 | |
| Bit time on bus (CANH − CANL pin) | tbit(Vi(diff)) | 155 | 210 | ns | tbit(TxD) = 200 ns (Note 14) | 9 | |
| Receiver timing symmetry | trec | -65 | 40 | ns | tbit(TxD) = 500 ns (Note 14) | 9 | |
| Receiver timing symmetry | trec | -45 | 15 | ns | tbit(TxD) = 200 ns (Note 14) | 9 | |
| Shutdown junction temperature | TJ(sd) | 160 | 180 | 200 | °C | Junction temperature rising | 9 |
| Supply voltage | VSUP | -0.3 | 6 | V | VCC, VIO | 6 | |
| DC voltage at pin CANH | VCANH | -42 | 42 | V | 0 < VCC < 5.5 V; no time limit | 6 | |
| DC voltage at pin CANL | VCANL | -42 | 42 | V | 0 < VCC < 5.5 V; no time limit | 6 | |
| DC voltage between CANH and CANL | VCANH − CANL | -42 | 42 | V | 6 | ||
| DC voltage at pin TxD, RxD, S | VI/O | -0.3 | 6 | V | 6 | ||
| Electrostatic discharge voltage at all pins, Component HBM | VesdHBM | -6 | 6 | kV | Component HBM (Note 3) | 6 | |
| Electrostatic discharge voltage at all pins, Component CDM | VesdCDM | -750 | 750 | V | Component CDM (Note 4) | 6 | |
| Electrostatic discharge voltage at pins CANH and CANL, System HBM | VesdIEC | -8 | 8 | kV | System HBM (Note 6) (Note 5) | 6 | |
| Storage temperature | Tstg | -55 | 150 | °C | 6 | ||
| Maximum junction temperature | TJ | -40 | 170 | °C | 6 | ||
| Thermal resistance junction-to-air, SOIC-8, 1S0P PCB | RJA | 131 | °C/W | Free air, 1S0P PCB (Note 9) | 7 | ||
| Thermal resistance junction-to-air, SOIC-8, 2S2P PCB | RJA | 81 | °C/W | Free air, 2S2P PCB (Note 10) | 7 |
CAD (KiCad official)
- Symbol:
NCV7357D13R2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncv7357d13r2g-etched.step/ncv7357d13r2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncv7357d13r2g.step/ncv7357d13r2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (16 pp, sha256
0bf0cc6041cb736e, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).