component
NCV7240BDPR2G
Public Made by Adomby adom
onsemi Power Distribution Switches, SSOP-24-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCV7240BDPR2G
onsemi · Power Distribution Switches · SSOP-24-150mil
NCV7240BDPR2G from onsemi, in a SSOP-24-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground. |
| 2 | GND | power_in | Ground. |
| 3 | OUT1 | output | Channel 1 low-side drive output that requires an external pull-up device for operation. |
| 4 | OUT2 | output | Channel 2 low-side drive output that requires an external pull-up device for operation. |
| 5 | OUT3 | output | Channel 3 low-side drive output that requires an external pull-up device for operation. |
| 6 | OUT4 | output | Channel 4 low-side drive output that requires an external pull-up device for operation. |
| 7 | OUT5 | output | Channel 5 low-side drive output that requires an external pull-up device for operation. |
| 8 | OUT6 | output | Channel 6 low-side drive output that requires an external pull-up device for operation. |
| 9 | OUT7 | output | Channel 7 low-side drive output that requires an external pull-up device for operation. |
| 10 | OUT8 | output | Channel 8 low-side drive output that requires an external pull-up device for operation. |
| 11 | GND | power_in | Ground. |
| 12 | GND | power_in | Ground. |
| 13 | VDD | power_in | Digital power supply for the SO output, 3.3 V or 5 V. |
| 14 | IN4 | input | Parallel control input for OUT4 and OUT8; ground if unused for best EMI performance, or leave open for the internal 120 kΩ pull-down to hold it low. |
| 15 | IN3 | input | Parallel control input for OUT3 and OUT7; ground if unused for best EMI performance, or leave open for the internal 120 kΩ pull-down to hold it low. |
| 16 | IN2 | input | Parallel control input for OUT2 and OUT6; ground if unused for best EMI performance, or leave open for the internal 120 kΩ pull-down to hold it low. |
| 17 | IN1 | input | Parallel control input for OUT1 and OUT5; ground if unused for best EMI performance, or leave open for the internal 120 kΩ pull-down to hold it low. |
| 18 | LHI | input | Active-high limp-home input that powers up the device and enables the INx-controlled outputs while disabling OUT5-OUT8 and ignoring SPI input commands; has an internal 120 kΩ pull-down. |
| 19 | SO | output | SPI serial data output with its high voltage level referenced to pin VDD. |
| 20 | SCLK | input | SPI clock input with an internal 120 kΩ pull-down. |
| 21 | EN | input | Global enable, active high, with an internal 120 kΩ pull-down. |
| 22 | SI | input | SPI serial data input with an internal 120 kΩ pull-down. |
| 23 | CSB | input | SPI chip select bar with an internal 120 kΩ pull-up to VDD. |
| 24 | VDDA | power_in | Analog power supply input, 5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SSOP-24-150mil |
| Category | Power Management (PMIC) |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Current (VDDA) | IVDDA_ON | 3 | 5 | mA | ON Mode (All Channels On) | 6 | |
| Quiescent Current (VDDA) Global Standby Mode, TJ = 25°C | IVDDA_GS_25 | 32 | µA | SI = SCLK = 0 V, CSB = VDD, TJ = 25°C | 6 | ||
| Quiescent Current (VDDA) Global Standby Mode, TJ = 150°C | IVDDA_GS_150 | 40 | µA | SI = SCLK = 0 V, CSB = VDD, TJ = 150°C | 6 | ||
| Quiescent Current (VDDA) Low Iq Mode, TJ = 25°C | IVDDA_LO_25 | 10 | µA | SI = SCLK = EN = 0 V, CSB = VDD, TJ = 25°C | 6 | ||
| Quiescent Current (VDDA) Low Iq Mode, TJ = 150°C | IVDDA_LO_150 | 20 | µA | SI = SCLK = EN = 0 V, CSB = VDD, TJ = 150°C | 6 | ||
| Quiescent Current (VDD) Global Standby Mode, TJ = 25°C | IVDD_GS_25 | 20 | µA | CSB = VDD = VDDA, fSCLK = 0 Hz, TJ = 25°C | 6 | ||
| Quiescent Current (VDD) Global Standby Mode, TJ = 150°C | IVDD_GS_150 | 40 | µA | CSB = VDD = VDDA, fSCLK = 0 Hz, TJ = 150°C | 6 | ||
| Quiescent Current (VDD) Low Iq Mode, TJ = 25°C | IVDD_LO_25 | 5 | µA | EN = 0 V, TJ = 25°C | 6 | ||
| Quiescent Current (VDD) Low Iq Mode, TJ = 150°C | IVDD_LO_150 | 20 | µA | EN = 0 V, TJ = 150°C | 6 | ||
| Power−on Reset threshold (VDDA), NCV7240B | POR_VDDA_rise | 3.6 | 3.85 | V | VDDA rising | 6 | |
| Power−on Reset threshold (VDDA), NCV7240B | POR_VDDA_fall | 3 | 3.3 | 3.5 | V | VDDA falling | 6 |
| Power−on Reset hysteresis (VDDA), NCV7240B | POR_VDD_hys | 150 | 200 | 350 | mV | 6 | |
| Power−on Reset threshold (VDD) | POR_VDDA_rise | 2.4 | 2.7 | V | VDD rising | 6 | |
| Power−on Reset Hysteresis (VDD) | POR_VDD_hys | 75 | 100 | 240 | mV | 6 | |
| Thermal Shutdown | TSD | 150 | 175 | 200 | °C | Not ATE tested | 6 |
| Output Transistor RDS(on) | RDS(on) | 1.5 | 3 | Ω | IOUTx = 180 mA | 6 | |
| Overload Detection Current | IOL | 0.6 | 0.95 | 1.3 | A | 6 | |
| Output Leakage, 25°C | Ileak_typ | 1 | µA | OUTx = 13.5 V, 25°C | 6 | ||
| Output Leakage | Ileak_temp | 5 | µA | OUTx = 13.5 V | 6 | ||
| Output Leakage | Ileak_HV | 10 | µA | OUTx = 35 V | 6 | ||
| Output Clamp Voltage | CLAMP | 36 | 40 | 44 | V | VDD = 0 V to 5.5 V, VDDA = 0 V to 5.5 V, IOUTx = 50 mA | 6 |
| Output Body Diode Voltage | BODY | 1.5 | V | IOUTx = −180 mA | 6 | ||
| Open Load Detection Threshold Voltage (Vol) | OPEN_V | 1 | 1.75 | 2.5 | V | 6 | |
| Open Load Diagnostic Sink Current (Iol) | OPEN_I | 20 | 60 | 100 | µA | 1 V < OUTx < 13.5 V, Output Disabled | 6 |
| Enable (EN) wake−up time | tWU | 200 | µs | CSB = 0 V, EN going high 80% to SO active | 7 | ||
| Serial Control Output turn−on time, All Channels | tSPI_ON | 30 | 50 | µs | CSB going high 80% to OUTx going low 20%, Vbat = 13.5 V, IDS = 180 mA resistive load | 7 | |
| Serial Control Output turn−off time, All Channels | tSPI_OFF | 30 | 50 | µs | CSB going high 80% to OUTx going high 80%, Vbat = 13.5 V, IDS = 180 mA resistive load | 7 | |
| Over Load Shut−Down Delay Time | tOVER | 3 | 15 | 50 | µs | 7 | |
| Open Load Detection Time | tOPEN | 30 | 115 | 200 | µs | 7 | |
| Digital Input Threshold (CSB, SI, SCLK, LHI, EN, INx) | LOGIC_V | 0.8 | 1.4 | 2 | V | 7 | |
| Digital Input Hysteresis (CSB, SI, SCLK, INx) | LOGIC_H1 | 50 | 175 | 300 | mV | 7 | |
| Digital Input Hysteresis (LHI, EN) | LOGIC_H2 | 150 | 400 | 800 | mV | 7 | |
| Input Pulldown Resistance (SI, SCLK, LHI, EN, INx) | RI_PD | 50 | 120 | 190 | kΩ | Inx = SI = SCLK = LHI = EN = VDD | 7 |
| Input Pullup Resistance (CSB) | RI_PU | 50 | 120 | 190 | kΩ | CSB = 0 V | 7 |
| SO, Output Low | SO_LO | 0.6 | V | I(out) = 2.0 mA | 7 | ||
| SCLK Frequency | freq | 5 | MHz | 7 | |||
| SCLK Clock Period | I/f | 200 | ns | 7 | |||
| SCLK High Time | tSCLK_HI | 85 | ns | Figure 5, #1 | 7 | ||
| SCLK Low Time | tSCLK_LO | 85 | ns | Figure 5, #2 | 7 | ||
| SI Setup Time | tSI_SU | 50 | ns | Figure 5, #11 | 7 | ||
| SI Hold Time | tSI_hold | 50 | ns | Figure 5, #12 | 7 | ||
| CSB Setup Time | tCSB_SU | 100 | ns | Figure 5, #5, 6 | 7 | ||
| Operating Current (VDD) | IVDD_ON | 0.5 | mA | EN = high, SCLK = Inx = 0 V, CSB = VDD = VDDA − 0.3 | 6 | ||
| Supply Input Voltage (VDDA, VDD), DC | VDDA, VDD | -0.3 | 5.5 | V | DC | 5 | |
| Digital I/O pin voltage (EN, LHI, Inx, CSB, SCLK, SI) | -0.3 | 5.5 | V | 5 | |||
| High Voltage Pins (OUTx), DC | OUTx | -0.3 | 36 | V | DC | 5 | |
| High Voltage Pins (OUTx), Peak Transient | OUTx | 44 | V | Peak transient, Note 1 (internally limited) | 5 | ||
| Output Current (OUTx) | OUTx | -1 | 1.3 | A | 5 | ||
| Clamping Energy, Maximum (single pulse) | 75 | mJ | Single pulse | 5 | |||
| Operating Junction Temperature Range | TJ | -40 | 150 | °C | 5 | ||
| Storage Temperature Range | TSTG | -55 | 150 | °C | 5 | ||
| ESD Capability, Human Body Model (OUTx pins) | -4000 | 4000 | V | Human body model (100 pF, 1.5 k), OUTx pins | 5 | ||
| ESD Capability, Human Body Model (all other pins) | -2000 | 2000 | V | Human body model (100 pF, 1.5 k), all other pins | 5 | ||
| ESD Capability, Machine Model | -200 | 200 | V | Machine Model (200 pF) | 5 | ||
| Supply voltage VDDA | VDDA | 4.5 | 5.5 | V | EC header: 3.0 V < VDD < VDDA, −40°C TJ 150°C; Note 7 reduced performance down to 4 V | 6 | |
| Supply voltage VDD | VDD | 3 | V | EC header: 3.0 V < VDD < VDDA | 6 | ||
| Package Thermal Resistance, Junction-to-Ambient (1s0p + 600 mm2 Cu) | 68 | °C/W | Note 4 | 5 | |||
| Package Thermal Resistance, Junction-to-Ambient (2s2p) | 62 | °C/W | Notes 4 and 5 | 5 | |||
| Package Thermal Resistance, Junction-to-Pin (pins 1, 2, 11, 12) | 30 | °C/W | Note 6 | 5 |
CAD (KiCad official)
- Symbol:
NCV7240BDPR2G - Footprint:
Package_SO:SSOP-24_5.3x8.2mm_P0.65mm - 3D model: SSOP-24-150mil (KiCad packages3D, STEP)
- 3D model files:
ncv7240bdpr2g-etched.step/ncv7240bdpr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncv7240bdpr2g.step/ncv7240bdpr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (29 pp, sha256
93e409890a40113b, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).