component
NCV68061SNAIT1G
Public Made by Adomby adom
onsemi Gate Drive ICs, TSOP-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownNCV68061SNAIT1G
onsemi · Gate Drive ICs · TSOP-6
NCV68061SNAIT1G from onsemi, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | Not connected and not internally bonded; can be left floating or connected to GND on the PCB. |
| 2 | GND | power_in | Ground potential. |
| 3 | EN | input | Enable input with 3.3 V logic compatible thresholds; high level enables the chip, connect to Source pin if enable function is not required. |
| 4 | D | passive | Cathode of the diode and inverting input of the internal comparator; bypass directly to GND with a ceramic capacitor and connect to the Drain of the external NMOS (Ideal Diode mode) or to GND (Reverse Polarity Protection mode). |
| 5 | G | output | Charge pump output with discharge function; connect to the Gate of the external NMOS. |
| 6 | S | power_in | Anode of the diode, input supply voltage pin (3 V to 32 V recommended) and non-inverting input of the internal comparator; bypass directly to GND with a ceramic capacitor and connect to the Source of the external NMOS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSOP-6 |
| Category | Power Management |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Source Voltage DC | VS | -18 | 45 | V | 3 | ||
| Load Dump Suppressed (Source, Drain, Gate, Enable) | Us* | 60 | V | Load Dump Test B, ISO 16750-2 | 3 | ||
| Test Pulse 1 (Source, Gate, Enable) | Us | -40 | V | ISO 7637-2 | 3 | ||
| Gate Voltage | VG | -18 | 45 | V | 3 | ||
| Gate to Source Voltage | VGS | -0.3 | 19 | V | 3 | ||
| Drain Voltage | VD | -5 | 45 | V | 3 | ||
| Source to Drain Voltage DC | VSD | -45 | 45 | V | 3 | ||
| Source to Drain Voltage transient | VSD | -60 | V | Test Pulse 1 | 3 | ||
| Enable Voltage | VEN | -18 | 45 | V | 3 | ||
| Operating Junction Temperature | TJ | -40 | 150 | °C | 3 | ||
| Storage Temperature | TSTG | -55 | 150 | °C | 3 | ||
| ESD Capability, Human Body Model | ESDHBM | -2 | 2 | kV | 3 | ||
| ESD Capability, Charged Device Model | ESDCDM | -1 | 1 | kV | 3 | ||
| Source Voltage | VS | 3 | 32 | V | 3 | ||
| Junction Temperature | TJ | -40 | 150 | °C | 3 | ||
| Thermal Resistance, Junction-to-Ambient | RθJA | 199.1 | °C/W | 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state) | 3 | ||
| Thermal Reference, Junction-to-Case Top | ΨJT | 57.3 | °C/W | 80 x 80 x 1.6 mm single layer FR4 board (645 sq mm, 1 oz. Cu, steady state) | 3 | ||
| Undervoltage Lockout, VS rising | VS_UVLO | 3 | 3.3 | 3.5 | V | VS rising | 4 |
| Undervoltage Lockout, VS falling (Gate Discharge) | VS_UVLO | 3.2 | V | VS falling (Gate Discharge) | 4 | ||
| Gate to Source Charged Voltage | VGS | 3 | 4 | V | VS = 4 V | 4 | |
| Gate to Source Charged Voltage | VGS | 9 | 11.4 | 15 | V | VS ≥ 8 V | 4 |
| Source to Drain Voltage Threshold, Gate Charge | Vth(SD) | 100 | 140 | 220 | mV | VSD rising | 4 |
| Source to Drain Voltage Threshold, Gate Discharge | Vth(SD) | -40 | -10 | 0 | mV | VSD falling | 4 |
| Gate Charge Current | IG_Charge | 70 | 105 | µA | VGS = 0 V, VSD = 220 mV, VS = 4 V | 4 | |
| Gate Charge Current | IG_Charge | 170 | 325 | µA | VGS = 0 V, VSD = 220 mV, VS = 13.5 V | 4 | |
| Discharge Switch RDS(on) | RDS(on) | 1 | 2.2 | 5 | Ω | VGS = 100 mV, VSD ≤ -100 mV | 4 |
| Response Time | trt_OFF | 0.2 | 0.6 | µs | VGS = 10 V, VS = 13.5 V, VSD = step from 250 mV to -150 mV | 4 | |
| Disable Current | IDIS | 5 | µA | VEN = 0 V | 4 | ||
| Quiescent Current | Iq | 215 | 295 | µA | IG = 0 mA, VSD = 220 mV (CP active) | 4 | |
| Enable Input Threshold Voltage, Logic Low | Vth(EN) | 0.99 | 1.55 | V | VGS ≤ 0.1 V | 4 | |
| Enable Input Threshold Voltage, Logic High | Vth(EN) | 1.7 | 2.31 | V | VGS ≥ 4.9 V | 4 | |
| Enable Input Current, Logic High | IEN_ON | 12 | µA | VEN = 13.5 V | 4 | ||
| Enable Input Current, Logic High | IEN_ON | 3.5 | 5 | µA | VEN = 5 V | 4 | |
| Enable Input Current, Logic Low | IEN_OFF | 0.01 | 1 | µA | VEN = 0 V | 4 | |
| Gate Discharge Peak Current | IG_Disch | 1.85 | A | VGS = 10 V, VSD ≤ -100 mV | 4 | ||
| Gate to Source Static Resistance | 1.05 | MΩ | 4 |
CAD (KiCad official)
- Symbol:
NCV68061SNAIT1G - Footprint:
Package_SO:TSOP-6_1.65x3.05mm_P0.95mm - 3D model: TSOP-6 (KiCad packages3D, STEP)
- 3D model files:
ncv68061snait1g-etched.step/ncv68061snait1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncv68061snait1g.step/ncv68061snait1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
3e70c87cd7e11e02, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).