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Contents

README

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NCV59745AMW100TAG

onsemi · Linear Voltage Regulators (LDO) · QFN-20-EP(4x4)

NCV59745AMW100TAG from onsemi, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Regulated output voltage; the datasheet recommends an output capacitor of at least 10 µF (effective value).
2 SNS input Output voltage sense input that must not be left floating; absolute maximum VSNS is −0.3 V to +6 V.
3 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
4 PG output Open-drain, active-high power-good output that goes high-impedance when VOUT exceeds the PG trip threshold; use a 10 kΩ to 100 kΩ pull-up to a supply up to 5.5 V (may be higher than VIN), or leave floating if not used.
5 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
6 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
7 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
8 GND power_in Ground pin that must be connected to ground.
9 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
10 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
11 NC unconnected No connection; a true NC pin that can be left floating or connected to GND for better thermal contact to the PCB top-side plane.
12 BIAS power_in Bias input for the error amplifier, reference and internal control circuits; recommended range is VOUT + 1.6 V to 5.5 V.
13 SS passive Soft-start pin; a capacitor to ground sets the soft-start time, with a maximum recommended CSS of 1 µF.
14 EN input Enable pin: driving high enables the regulator and driving low (≤ 0.4 V) puts it in shutdown; it must not be left floating.
15 IN power_in Unregulated voltage input to the device; recommended VIN range is VOUT + VDO to 5.5 V, absolute maximum −0.3 V to +6 V.
16 IN power_in Unregulated voltage input to the device; recommended VIN range is VOUT + VDO to 5.5 V, absolute maximum −0.3 V to +6 V.
17 IN power_in Unregulated voltage input to the device; recommended VIN range is VOUT + VDO to 5.5 V, absolute maximum −0.3 V to +6 V.
18 GND power_in Ground pin that must be connected to ground.
19 OUT power_out Regulated output voltage; the datasheet recommends an output capacitor of at least 10 µF (effective value).
20 OUT power_out Regulated output voltage; the datasheet recommends an output capacitor of at least 10 µF (effective value).
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer onsemi
Package QFN-20-EP(4x4)
Category Power Management ICs
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range (absolute) VIN -0.3 6 V 3
Bias voltage range (absolute) VBIAS -0.3 6 V 3
Enable voltage range (absolute) VEN -0.3 6 V 3
Power-good voltage range (absolute) VPG -0.3 6 V 3
PG sink current IPG 0 1.5 mA 3
SS pin voltage range (absolute) VSS -0.3 6 V Printed as (VBIAS + 0.3) ≤ 6 V 3
Output sense pin voltage range (absolute) VSNS -0.3 6 V 3
Output voltage range (absolute) VOUT -0.3 6 V Printed as (VIN + 0.3) ≤ 6 V 3
Maximum junction temperature TJMAX 150 °C 3
Storage junction temperature range TSTG -55 150 °C 3
ESD capability, human body model ESDHBM 2000 V AEC-Q100-002 3
ESD capability, charged device model ESDCDM 1000 V AEC-Q100-011 3
Latch-up current maximum rating -100 100 mA AEC-Q100-004 3
Input voltage (recommended) VIN 5.5 V Printed minimum is VOUT + VDO 3
Bias voltage (recommended) VBIAS 5.5 V Printed minimum is VOUT + 1.6 3
Junction temperature (recommended) TJ -40 125 °C 3
Input voltage range VIN 5.5 V Printed minimum is VOUT + VDO 4
Bias pin voltage range VBIAS 5.5 V Printed minimum is VOUT + 1.4 4
Undervoltage lockout, VBIAS rising UVLO 1.2 1.5 2 V VBIAS rising 4
Output voltage accuracy VOUT -1 0.3 1 % 2.4 V ≤ VBIAS ≤ 5.25 V, VOUT + 1.6 V ≤ VBIAS; 50 mA ≤ IOUT ≤ 3.0 A; typ printed as ±0.3 4
VIN dropout voltage VDO 105 195 mV IOUT = 3.0 A, VBIAS − VOUT(NOM) = 1.6 V 4
VBIAS dropout voltage 1.2 1.4 V IOUT = 3.0 A, VIN = VBIAS 4
Current limit ICL 3.5 4.3 7 A VOUT = 80% x VOUT(NOM) 4
Bias pin current IBIAS 1.3 2 mA 0 mA ≤ IOUT ≤ 3.0 A 4
VBIAS shutdown current IBSHDN 1 15 µA VEN ≤ 0.4 V 4
VIN shutdown current IINSHDN 1 15 µA VEN ≤ 0.4 V, VOUT = 0 V 4
Sense pin current ISNS -250 95 250 nA 0 mA ≤ IOUT ≤ 3.0 A 4
Enable input high level VEN, HI 1.1 5.5 V 4
Enable input low level VEN, LO 0 0.4 V 4
Enable pin current IEN 0.3 1 µA VEN = 5 V 4
PG trip threshold, VOUT decreasing VIT− 82 88 93 %VOUT VOUT decreasing 4
PG trip threshold, VOUT increasing VIT+ 83 91 96 %VOUT VOUT increasing 4
PG leakage current IPG, LKG 0.03 1 µA VPG = 5.25 V, VOUT > VIT 4
Junction-to-ambient thermal resistance RJA 40 °C/W JEDEC JESD51 high-K board, natural convection 3
Junction-to-board thermal resistance RJB 3.6 °C/W 3
Junction-to-case (top) thermal resistance RJC(top) 27 °C/W 3
Junction-to-case (bottom) thermal resistance RJC(bot) 3.6 °C/W 3
Characterisation parameter, junction-to-top JT 1 °C/W 3
Characterisation parameter, junction-to-board JB 3.5 °C/W 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper pins directly in the device PCB copper layer, not through 9

CAD (KiCad official)

  • Symbol: NCV59745AMW100TAG
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ncv59745amw100tag-etched.step / ncv59745amw100tag-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv59745amw100tag.step / ncv59745amw100tag.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 0c2c07af4a798eb9, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF