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NCV57201DR2G

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onsemi Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV57201DR2G

onsemi · Gate Drivers · SOIC-8

NCV57201DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Low-side and main power supply that must be bypassed close to GND, with UVLO1 enabling operation once VDD exceeds VUVLO1-OUT-ON (typically 12.5 V) and a recommended maximum of 20 V.
2 HIN input High-side non-inverting gate driver input with an internal 125 kΩ pull-down, 3.3 V logic thresholds for input voltage up to VDD, and a minimum pulse width required before HO reacts.
3 LIN input Low-side non-inverting gate driver input with an internal 125 kΩ pull-down, 3.3 V logic thresholds for input voltage up to VDD, and a minimum pulse width required before LO reacts.
4 GND power_in Logic ground and low-side driver return for the device.
5 LO output Low-side driver output that provides gate drive and source/sink current to the IGBT and is actively pulled low during startup and UVLO1 conditions.
6 VS power_in Bootstrap return and high-side floating supply offset, with the recommended operating range of −800 V to 800 V (absolute maximum ±900 V).
7 HO output Galvanically isolated high-side driver output that provides gate drive and source/sink current to the IGBT and is actively pulled low during startup and UVLOx conditions.
8 VB power_in Bootstrap or high-side floating power supply that must be bypassed to VS close to the pin, with UVLO2 enabling operation once VBS exceeds VUVLO2-OUT-ON (typically 11.5 V) and VBS up to VS+20 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low-Side Supply Voltage (VDD) absolute maximum VDD -0.3 25 V 4
High-Side Floating Supply Voltage (VBS) absolute maximum VBS -0.3 25 V 4
High-Side Offset Voltage (VS) absolute maximum VS -900 900 V see Figure 2 4
High-Side Supply Voltage (VB) absolute maximum VB -900 900 V 4
Low-Side Output Voltage (LO) absolute maximum minimum VLO -0.3 V Maximum is VDD+0.3 V (expression, see review) 4
Logic Input Voltage (HIN, LIN) absolute maximum minimum VIN -0.3 V Maximum is VDD+0.3 V (expression, see review) 4
Allowable Offset Voltage Slew Rate dVS/dt -100 100 V/ns see Figure 31 4
Maximum Junction Temperature TJ(max) -40 150 °C 4
Storage Temperature Range TSTG -65 150 °C 4
Power Dissipation 1 PD1 0.87 W 100 mm2, 2 oz. copper, 1 surface layer (Note 2) 4
Power Dissipation 2 PD2 1.41 W 100 mm2, 2 oz. copper, 2 surface layers and 2 internal power plane layers (Note 2) 4
ESD Capability, Human Body Model ESDHBM -4 4 kV per AEC-Q100-002 (Note 3) 4
ESD Capability, Charged Device Model ESDCDM -2 2 kV per AEC-Q100-011 (Note 3) 4
Moisture Sensitivity Level MSL 1 4
Lead Temperature Soldering Reflow (SMD styles, Pb-Free versions) TSLD 260 °C Note 4 4
Low-Side Supply Voltage (VDD) recommended operating maximum VDD 20 V 4
High-Side Offset Voltage (VS) recommended operating VS -800 800 V see Figure 2 4
Ambient Temperature TA -40 125 °C 4
Thermal Resistance, Junction-to-Air RJA 167 °C/W 100 mm2, 1 oz Copper, 1 Surface Layer 4
Thermal Resistance, Junction-to-Air RJA 98 °C/W 650 mm2, 1 oz Copper, 2 Surface Layers and 2 Internal Power Plane Layers 4
VBS Supply Under Voltage Output Enabled VUVLO2-OUT-ON 11 11.5 12 V 5
VBS Supply Under Voltage Output Disabled VUVLO2-OUT-OFF 10 10.5 11 V 5
VBS Supply Voltage Output Enabled/Disabled Hysteresis VUVLO2-HYST 0.4 1 1.2 V 5
VDD Supply Under Voltage Output Enabled VUVLO1-OUT-ON 12 12.5 13 V 5
VDD Supply Under Voltage Output Disabled VUVLO1-OUT-OFF 11 11.5 12 V 5
VDD Supply Voltage Output Enabled/Disabled Hysteresis VUVLO1-HYST 0.5 1 1.2 V 5
Leakage Current Between VS and GND (TA = 25°C) IHV_LEAK1 20 200 nA VS = ±800 V, TA = 25°C 5
Leakage Current Between VS and GND (TA = -40°C to 125°C) IHV_LEAK2 600 nA VS = ±800 V, TA = −40°C to 125°C 5
Quiescent Current VBS Supply (VB Only), HO Low IQBS1 260 325 A HO = Low 5
Quiescent Current VBS Supply (VB Only), HO High IQBS2 330 440 A HO = High 5
Quiescent Current VDD Supply (VDD Only), input float IQDD1 380 440 A VLIN = Float, VHIN = 0 V 5
Quiescent Current VDD Supply (VDD Only), LIN high IQDD2 440 510 A VLIN = 3.3 V, VHIN = 0 V 5
Quiescent Current VDD Supply (VDD Only), HIN high IQDD3 2.4 3 mA VLIN = 0 V, VHIN = 3.3 V 5
Low Level Input Voltage VIL 0.9 V 5
High Level Input Voltage VIH 2.4 V 5
Logic 1 Input Bias Current (LIN, HIN at 3.3 V) ILIN1+, IHIN1+ 25 50 A VLIN = 3.3 V, VHIN = 3.3 V 5
Logic 1 Input Bias Current (LIN, HIN at 20 V) ILIN2+, IHIN2+ 100 150 A VLIN = 20 V, VHIN = 20 V, VDD = VBS = 20 V 5
Logic 0 Input Bias Current ILIN-, IHIN- 40 100 nA VLIN = 0 V, VHIN = 0 V 5
Output Low State (TA = 25°C) VOL1 0.2 0.3 V ISINK = 200 mA, TA = 25°C 5
Output Low State (TA = -40°C to 125°C) VOL2 0.5 V ISINK = 200 mA, TA = −40°C to 125°C 5
Output High State (TA = 25°C) VOH1 14.4 14.5 V ISOURCE = 200 mA, TA = 25°C 5
Output High State (TA = -40°C to 125°C) VOH2 14 V ISOURCE = 200 mA, TA = −40°C to 125°C 5
Clamping Voltage (VHO-VB)/(VLO-VDD) VCLAMP-OUT 0.8 1.3 V IHO = 100 mA, ILO = 100 mA (pulse test, tCLPmax = 10 s) 6
HO High Propagation Delay tPD-ON-H 50 70 110 ns CLOAD = 1 nF, VIH to 10% of Output Change for PW > 150 ns 6
HO Low Propagation Delay tPD-OFF-H 50 70 110 ns CLOAD = 1 nF, VIL to 90% of Output Change for PW > 150 ns 6
Propagation Delay Distortion (HS) tDISTORT-H -25 0 25 ns PW > 150 ns 6
LO High Propagation Delay tPD-ON-L 50 70 110 ns CLOAD = 1 nF, VIH to 10% of Output Change for PW > 150 ns 6
LO Low Propagation Delay tPD-OFF-L 50 70 110 ns CLOAD = 1 nF, VIL to 90% of Output Change for PW > 150 ns 6
Propagation Delay Distortion (LS) tDISTORT-L -25 0 25 ns PW > 150 ns 6
High Propagation Delay Distortion between High and Low Sides tDISTORT-HL-H -25 0 25 ns PW > 150 ns 6
Low Propagation Delay Distortion between High and Low Sides tDISTORT-HL-L -25 0 25 ns PW > 150 ns 6
Minimum Pulse Width Filtering Time tMIN1, tMIN2 10 40 ns TA = 25°C 6

CAD (KiCad official)

  • Symbol: NCV57201DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv57201dr2g-etched.step / ncv57201dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv57201dr2g.step / ncv57201dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (18 pp, sha256 5f42c735d5255643, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF