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NCV4275CDS50R4G

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onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TO-263-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Contents

README

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NCV4275CDS50R4G

onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TO-263-5

NCV4275CDS50R4G from onsemi, in a TO-263-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I power_in Input; battery supply input voltage (operating 5.5 V to 42 V for the 5.0 V version, absolute max -42 V to 45 V), bypass to ground with a ceramic capacitor.
2 RO output Reset Output; open collector active reset, accurate when I > 1.0 V, needs external pull-up (typically 5.0 k to VQ), max 25 V and ±5.0 mA.
3 GND power_in Ground; pin 3 is internally connected to the tab.
4 D passive Reset Delay; timing capacitor to GND sets the reset delay time (47 nF gives 16 ms typical).
5 Q power_out Output; ±2.0% 5.0 V, 450 mA output, bypass with 22 µF capacitor with ESR < 4.5 Ω (5.0 V version).
6 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer onsemi
Package TO-263-5
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage (5.0 V version) VQ 4.9 5 5.1 V 100 µA ≤ IQ ≤ 400 mA; 6.0 V ≤ VI ≤ 28 V (5.0 V Version) 4
Output Voltage (5.0 V version, wide input) VQ 4.9 5 5.1 V 100 µA ≤ IQ ≤ 200 mA; 6.0 V ≤ VI ≤ 40 V (5.0 V Version) 4
Output Current Limitation IQ 450 650 mA VQ = 0.9 x VQ,typ 4
Quiescent Current Iq 135 150 µA IQ = 1.0 mA, TJ = 25°C 4
Quiescent Current Iq 150 200 µA IQ = 1.0 mA 4
Quiescent Current Iq 10 15 mA IQ = 250 mA 4
Quiescent Current Iq 23 35 mA IQ = 400 mA 4
Dropout Voltage Vdr 250 500 mV IQ = 300 mA; Vdr = VI − VQ 4
Load Regulation VQ -30 15 30 mV IQ = 5.0 mA to 400 mA 4
Line Regulation VQ -15 5 15 mV VI = 8.0 V to 32 V, IQ = 5.0 mA 4
Reset Switching Threshold (5.0 V version) VQ,rt 90 93 96 % Vout Vout decreasing; Vin > 5.5 V 4
Reset Output Low Voltage VROL 0.2 0.4 V Rext ≥ 5.0 k, VQ ≥ 1.0 V 4
Reset Output Leakage Current IROH 0 10 µA VROH = 5.0 V 4
Reset Charging Current ID,C 3 5.5 9 µA VD = 1.0 V 4
Upper Timing Threshold VDU 1.5 1.8 2.2 V 4
Lower Timing Threshold VDL 0.2 0.4 0.7 V 4
Reset Delay Time trd 10 16 22 ms CD = 47 nF 4
Reset Reaction Time trr 1.5 4 s CD = 47 nF 4
Thermal Shutdown Temperature TSD 150 210 °C Guaranteed by design, not tested in production (note 8) 4
Input Voltage VI -42 45 V 2
Input Peak Transient Voltage VI 45 V 2
Output Voltage VQ -1 16 V 2
Reset Output Voltage VRO -0.3 25 V 2
Reset Output Current IRO -5 5 mA 2
Reset Delay Voltage VD -0.3 7 V 2
Reset Delay Current ID -2 2 mA 2
ESD Susceptibility Human Body Model ESDHBM 4 kV AEC-Q100-002 2
ESD Susceptibility Machine Model ESDMM 200 V AEC-Q100-003 2
ESD Susceptibility Charge Device Model ESDCDM 1000 V AEC-Q100-011 2
Junction Temperature TJ -40 150 °C 2
Storage Temperature Tstg -55 150 °C 2
Lead Temperature Soldering Reflow (Peak) TSLD 265 °C Lead Free, 60 sec to 150 sec above 217°C 2
Input Voltage Operating Range (5.0 V output) VI 5.5 42 V 5.0 V Output 2
Junction Temperature Operating Range TJ -40 150 °C 2
Junction-to-Tab Thermal Resistance (D2PAK) RJT 4.5 °C/W 0.4 sq. in. spreader board (Note 5) 3
Junction-to-Tab Thermal Resistance (D2PAK) RJT 4.8 °C/W 1.2 sq. in. spreader board (Note 6) 3
Junction-to-Ambient Thermal Resistance (D2PAK) RJA 66 °C/W 0.4 sq. in. spreader board (Note 5) 3
Junction-to-Ambient Thermal Resistance (D2PAK) RJA 49 °C/W 1.2 sq. in. spreader board (Note 6) 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts Copper DPAK 5−Lead Figure 25. JA vs. Copper Spreader Area, 11

CAD (KiCad official)

  • Symbol: NCV4275CDS50R4G
  • Footprint: Package_TO_SOT_SMD:TO-263-5_TabPin6
  • 3D model: TO-263-5 (KiCad packages3D, STEP)
  • 3D model files: ncv4275cds50r4g-etched.step / ncv4275cds50r4g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv4275cds50r4g.step / ncv4275cds50r4g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (16 pp, sha256 572ffc2d9f1cc2f6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF