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NCV4254CPDSTR2G

Public Made by Adom

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onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV4254CPDSTR2G

onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

NCV4254CPDSTR2G from onsemi, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Vout power_out Tracker output voltage; connect a 2.2 µF capacitor with ESR < 5 (the ohm symbol is missing from the extracted text) to ground, and it may be connected directly or through a voltage divider for lower output voltages.
2 NC unconnected Not connected in the SOIC-8 EP package; the datasheet says to connect it to GND.
3 NC unconnected Not connected in the SOIC-8 EP package; the datasheet says to connect it to GND.
4 ST output Tracking regulator status output, open collector; connect via a pull-up resistor to a positive voltage rail, and a low signal indicates a fault condition at the regulator output.
5 EN/REF input Enable and reference input; a low signal disables the IC and a high signal enables it, with VEN/REF recommended at 2 V minimum, and the reference may be connected directly or through a voltage divider.
6 GND power_in Power supply ground.
7 NC unconnected Not connected in the SOIC-8 EP package; the datasheet says to connect it to GND.
8 Vin power_in Positive power supply input with a recommended range of 4 V to 45 V; connect a 0.1 µF capacitor to ground.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Voltage DC Vin -20 45 V 3
Peak Transient Voltage (Load Dump) Vin 45 V Load dump (Note 2) 3
Output Voltage Vout -5 40 V 3
Enable / Reference Input Voltage DC VEN/REF -20 40 V 3
Status output Voltage (Status Output Version) DC VST -0.3 7 V 3
Maximum Junction Temperature TJ(max) -40 150 °C 3
Storage Temperature TSTG -55 150 °C 3
ESD Capability, Human Body Model ESDHBM -4 4 kV AEC-Q100-002 (Table 3, Note 3) 3
Input Voltage Vin 4 45 V 4
Enable / Reference Input Voltage VEN/REF 2 V 4
Junction Temperature TJ -40 150 °C 4
Thermal Resistance, Junction-to-Ambient, SOIC-8 EP RJA 75 °C/W Note 5: 645 mm2 (1 in2), 1 oz Cu, FR4 4
Thermal Reference, Junction-to-Case Top, SOIC-8 EP RJT 11.5 °C/W Note 5: 645 mm2 (1 in2), 1 oz Cu, FR4 4
Output Voltage Tracking Accuracy Vout -3 3 mV Vin = 5.7 V to 26 V, Iout = 0.1 mA to 60 mA, 2.5 V ≤ VEN/REF ≤ (VIN − 600 mV) 4
Output Voltage Tracking Accuracy Vout -10 10 mV Vin = 5.5 V to 26 V, Iout = 0.1 mA to 60 mA, VEN/REF = 5 V 4
Line Regulation Regline -5 5 mV Vin = 5.5 V to 32 V, Iout = 5 mA, VEN/REF = 5V 4
Load Regulation Regload -5 5 mV Iout = 0.1 mA to 70 mA, VEN/REF = 5 V 4
Dropout Voltage VDO 220 400 mV Iout = 70 mA, VEN/REF = 5 V 4
Disable Current, Stand-by Mode IDIS 0.01 5 µA VEN/REF ≤ 0.4 V, TJ ≤ 125°C 4
Quiescent Current, Iq = Iin − Iout Iq 65 80 µA Iout ≤ 0.1 mA, VEN/REF = 5 V 4
Quiescent Current, Iq = Iin − Iout Iq 1 2 mA Iout ≤ 70 mA, VEN/REF = 5 V 4
Current Limit ILIM 71 110 150 mA Vout = (VEN/REF, 0.1 V), VEN/REF = 5 V 4
Reverse Current Iout_rev -15 -10 mA Vin = 0 V, Vout = 32 V, VEN/REF = 5 V 4
Reverse Current at Negative Input Voltage Iin_rev -1 -0.2 mA Vin = −16 V, Vout = 0 V, VEN/REF = 5 V 4
Enable / Reference Input Threshold Voltage, Logic High Vth(EN/REF) 2 V Vout = 0 V, Iout ≤ 5 A, Tj ≤ 125°C; /Vout − VEN/REF/ < 10 mV 4
Enable / Reference Input Threshold Voltage, Logic Low Vth(EN/REF) 0.4 V Vout = 0 V, Iout ≤ 5 A, Tj ≤ 125°C; /Vout − VEN/REF/ < 10 mV 4
Enable / Reference Input Current IEN/REF 2 3 µA VEN/REF = 5 V 5
Enable / Reference Input Current if Input tied to GND IEN/REF 0.003 0.6 mA Vin = 0 V, VEN/REF = 5 V 5
Enable / Reference Internal Pull-Down Resistor REN/REF 1.7 2.2 3.3 MΩ 5
Status Switching Threshold, Undervoltage (relative to VEN/REF) Vout_UV -120 -77 -50 mV Vout decreasing; threshold = VEN/REF + printed value 5
Status Switching Threshold, Overvoltage (relative to VEN/REF) Vout_OV 50 77 120 mV Vout increasing; threshold = VEN/REF + printed value 5
Status reaction Time tST 10 23 33 µs 5
Status Output Low Voltage VST_low 0.4 V IST = 1 mA, Vin ≥ 4 V 5
Status Output Sink Current Limitation IST_max 1 mA VST = 0.8 V 5
Status Output Leakage Current IST_leak 2 µA Vout = VEN/REF, VST = 5 V 5
Thermal Shutdown Temperature TSD 151 175 200 °C 5

CAD (KiCad official)

  • Symbol: NCV4254CPDSTR2G
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: ncv4254cpdstr2g-etched.step / ncv4254cpdstr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv4254cpdstr2g.step / ncv4254cpdstr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (17 pp, sha256 6d682e1e389ebefd, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF