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ncv33172dr2g-etched.step ncv33172dr2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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page.json ncv33172dr2g: specified limits as data (metadata.characteristics, 29 rows from the datasheet) · Ray 19d ago
README.md ncv33172dr2g: specified limits as data (metadata.characteristics, 29 rows from the datasheet) · Ray 19d ago

NCV33172DR2G

onsemi · Operational Amplifier · SOIC-8

NCV33172DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Output 1 output Op-amp channel 1 output. All-NPN output stage; typical swing to within ~0.8 V of both rails with a 10 kΩ load; sources typ 5 mA, sinks typ 27 mA (min 15 mA); output short-circuit protected.
2 Inv. Input 1 input Inverting (−) input of op-amp channel 1. High-impedance Darlington PNP input stage; typ input bias current 20 nA, typ differential input resistance 300 MΩ, input capacitance 0.8 pF.
3 Noninv. Input 1 input Non-inverting (+) input of op-amp channel 1. Common-mode range extends from VEE up to (VCC − 1.8 V) at 25 °C; ESD diodes provide input protection on the dual/quad devices.
4 VEE power_in Negative supply / ground. Single-supply operation ties this to GND (VCC = 3.0 V to 44 V); split-supply operation uses ±1.5 V to ±22 V. Absolute-max supply span
5 Noninv. Input 2 input Non-inverting (+) input of op-amp channel 2. Same input characteristics as channel 1: CM range VEE to (VCC − 1.8 V), typ IB = 20 nA, 300 MΩ differential input resistance.
6 Inv. Input 2 input Inverting (−) input of op-amp channel 2. High-impedance Darlington PNP input stage; matches channel 1 for offset, bias, and noise characteristics (VIO typ 2.0 mV, en typ 32 nV/√Hz at 1 kHz).
7 Output 2 output Op-amp channel 2 output. Same drive as Output 1: capacitive drive capability 0 pF to 500 pF, GBW 1.8 MHz, SR 2.1 V/µs, channel separation typ 120 dB at 10 kHz.
8 VCC power_in Positive supply rail, 3.0 V to 44 V single-supply or +1.5 V to +22 V split-supply. Per-amplifier quiescent current typ 220 µA at ±15 V (typ 180 µA at +5 V). Decouple to VEE with a low-ESR capacitor placed adjacent to the pin.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Op-amp/Cmp
Pins 8

Ordering variants

  • NCV33172DR2G
  • NCV33172DR2GDG
  • NCV33172DR2GVDR2G
  • NCV33172DR2GVDG
  • NCV33172DR2GPG

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC/VEE -22 22 V Printed as ±22 V 3
Operating Junction Temperature TJ 150 °C 3
Storage Temperature Range Tstg -65 150 °C 3
Supply Operating Range 3 44 V Single supply (Features list); split supplies ±1.5 V to ±22 V also listed 1
Operating Ambient Temperature Range TA -40 125 °C Note 3: NCV3317x Tlow = −40°C, Thigh = +125°C 3
Input Offset Voltage VIO 2 4.5 mV VCM = 0 V; VCC = +15 V, VEE = −15 V, TA = +25°C 3
Input Offset Voltage VIO 2.5 5 mV VCM = 0 V; VCC = +5.0 V, VEE = 0 V, TA = +25°C 3
Input Offset Voltage VIO 6.5 mV VCM = 0 V; VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh 3
Input Bias Current IIB 20 100 nA VCM = 0 V; TA = +25°C 3
Input Bias Current IIB 200 nA VCM = 0 V; TA = Tlow to Thigh 3
Input Offset Current IIO 5 20 nA VCM = 0 V; TA = +25°C 3
Input Offset Current IIO 40 nA VCM = 0 V; TA = Tlow to Thigh 3
Large Signal Voltage Gain AVOL 50 500 V/mV VO = ±10 V, RL = 10 kΩ; TA = +25°C 3
Large Signal Voltage Gain AVOL 25 V/mV VO = ±10 V, RL = 10 kΩ; TA = Tlow to Thigh 3
Output Voltage Swing High VOH 3.5 4.3 V VCC = +5.0 V, VEE = 0 V, RL = 10 kΩ, TA = +25°C 3
Output Voltage Swing High VOH 13.6 14.2 V VCC = +15 V, VEE = −15 V, RL = 10 kΩ, TA = +25°C 3
Output Voltage Swing High VOH 13.3 V VCC = +15 V, VEE = −15 V, RL = 10 kΩ, TA = Tlow to Thigh 3
Output Voltage Swing Low VOL 0.05 0.15 V VCC = +5.0 V, VEE = 0 V, RL = 10 kΩ, TA = +25°C 3
Output Voltage Swing Low VOL -14.2 -13.6 V VCC = +15 V, VEE = −15 V, RL = 10 kΩ, TA = +25°C 3
Output Voltage Swing Low VOL -13.3 V VCC = +15 V, VEE = −15 V, RL = 10 kΩ, TA = Tlow to Thigh 3
Output Short Circuit Current Source ISC 3 5 mA Input Overdrive = 1.0 V, Output to Ground; TA = +25°C 3
Output Short Circuit Current Sink ISC 15 27 mA Input Overdrive = 1.0 V, Output to Ground; TA = +25°C 3
Common Mode Rejection Ratio CMRR 80 90 dB RS ≤ 10 k; TA = +25°C 3
Power Supply Rejection Ratio PSRR 80 100 dB RS = 100; TA = +25°C 3
Power Supply Current Per Amplifier ID 180 250 µA VCC = +5.0 V, VEE = 0 V, TA = +25°C 3
Power Supply Current Per Amplifier ID 220 250 µA VCC = +15 V, VEE = −15 V, TA = +25°C 3
Power Supply Current Per Amplifier ID 300 µA VCC = +15 V, VEE = −15 V, TA = Tlow to Thigh 3
Slew Rate SR 1.6 2.1 V/µs Vin = −10 V to +10 V, RL = 10 kΩ, CL = 100 pF; AV = +1 4
Gain Bandwidth Product GBW 1.4 1.8 MHz f = 100 kHz 4

CAD (KiCad official)

  • Symbol: NCV33172DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv33172dr2g-etched.step / ncv33172dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv33172dr2g.step / ncv33172dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (None pp, sha256 f1e9ff0b61491b0b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF