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NCV317LBDR2G
Public Made by Adomby adom
onsemi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCV317LBDR2G
onsemi · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
NCV317LBDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vin | power_in | Input supply pin; the input-to-output differential VI−VO must not exceed 40 Vdc per the maximum ratings. |
| 2 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA. |
| 3 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA; tied internally in parallel with pin 2 on the SOIC-8 package. |
| 4 | Adjust | passive | Adjustment pin that sets the output via Vout = Vref(1 + R2/R1) + IAdj·R2 with Vref of about 1.25 V; IAdj is controlled to less than 100 µA, and an optional CAdj to ground improves ripple rejection. |
| 5 | N.C. | unconnected | Marked N.C. on the package pinout; the datasheet specifies no function for this pin. |
| 6 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA. |
| 7 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA. |
| 8 | N.C. | unconnected | Marked N.C. on the package pinout; the datasheet specifies no function for this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Line Regulation | Regline | 0.01 | 0.04 | %/V | TA = 25°C, 3.0 V ≤ VI − VO ≤ 40 V | 3 | |
| Load Regulation (VO ≤ 5.0 V) | Regload | 5 | 25 | mV | 10 mA ≤ IO ≤ Imax, VO ≤ 5.0 V, TA = 25°C | 3 | |
| Load Regulation (VO ≥ 5.0 V) | Regload | 0.1 | 0.5 | % VO | 10 mA ≤ IO ≤ Imax, VO ≥ 5.0 V, TA = 25°C | 3 | |
| Adjustment Pin Current | IAdj | 50 | 100 | µA | 3 | ||
| Adjustment Pin Current Change | IAdj | 0.2 | 5 | µA | 2.5 V ≤ VI − VO ≤ 40 V, PD ≤ Pmax; 10 mA ≤ IO ≤ Imax | 3 | |
| Reference Voltage | Vref | 1.2 | 1.25 | 1.3 | V | 3.0 V ≤ VI − VO ≤ 40 V, PD ≤ Pmax; 10 mA ≤ IO ≤ Imax | 3 |
| Ripple Rejection (VO = 1.2 V) | RR | 60 | 80 | dB | VO = 1.2 V, f = 120 Hz | 3 | |
| Ripple Rejection (CAdj = 10 µF) | RR | 80 | dB | CAdj = 10 µF, VO = 10.0 V, f = 120 Hz | 3 | ||
| Long Term Stability | S | 0.3 | 1 | %/1.0k Hrs. | TJ = Thigh; TA = 25°C for endpoint measurements | 3 | |
| Temperature Stability | TS | 0.7 | % VO | Tlow ≤ TJ ≤ Thigh | 3 | ||
| Minimum Load Current to Maintain Regulation | ILmin | 3.5 | 10 | mA | VI − VO = 40 V | 3 | |
| RMS Noise | N | 0.003 | % VO | TA = 25°C, 10 Hz ≤ f ≤ 10 kHz | 3 | ||
| Thermal Shutdown | 180 | °C | 3 | ||||
| Input-Output Voltage Differential | VI−VO | 40 | Vdc | 2 | |||
| Maximum Junction Temperature | TJMAX | 150 | °C | 2 | |||
| Storage Temperature Range | Tstg | -65 | 150 | °C | 2 | ||
| Operating Junction Temperature Range (NCV, Tlow to Thigh) | TJ | -40 | 125 | °C | NCV317LBDR2G SOIC-8 ordering information note: Tlow = −40°C, Thigh = +125°C | 9 | |
| Thermal Resistance, Junction-to-Ambient (SOIC-8) | RθJA | 180 | °C/W | SOIC-8, minimum recommended pad size (Note 1) | 2 | ||
| Thermal Resistance, Junction-to-Case (SOIC-8) | RθJC | 45 | °C/W | SOIC-8 | 2 |
CAD (KiCad official)
- Symbol:
NCV317LBDR2G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ncv317lbdr2g-etched.step/ncv317lbdr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncv317lbdr2g.step/ncv317lbdr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (11 pp, sha256
146364af02ceebcc, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCV317LBDR2G
**onsemi** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
NCV317LBDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Vin | power_in | Input supply pin; the input-to-output differential VI−VO must not exceed 40 Vdc per the maximum ratings. |
| 2 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA. |
| 3 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA; tied internally in parallel with pin 2 on the SOIC-8 package. |
| 4 | Adjust | passive | Adjustment pin that sets the output via Vout = Vref(1 + R2/R1) + IAdj·R2 with Vref of about 1.25 V; IAdj is controlled to less than 100 µA, and an optional CAdj to ground improves ripple rejection. |
| 5 | N.C. | unconnected | Marked N.C. on the package pinout; the datasheet specifies no function for this pin. |
| 6 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA. |
| 7 | Vout | power_out | Regulated output pin, adjustable from 1.2 V to 37 V, supplying in excess of 100 mA. |
| 8 | N.C. | unconnected | Marked N.C. on the package pinout; the datasheet specifies no function for this pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Line Regulation | Regline | | 0.01 | 0.04 | %/V | TA = 25°C, 3.0 V ≤ VI − VO ≤ 40 V | 3 |
| Load Regulation (VO ≤ 5.0 V) | Regload | | 5 | 25 | mV | 10 mA ≤ IO ≤ Imax, VO ≤ 5.0 V, TA = 25°C | 3 |
| Load Regulation (VO ≥ 5.0 V) | Regload | | 0.1 | 0.5 | % VO | 10 mA ≤ IO ≤ Imax, VO ≥ 5.0 V, TA = 25°C | 3 |
| Adjustment Pin Current | IAdj | | 50 | 100 | µA | | 3 |
| Adjustment Pin Current Change | IAdj | | 0.2 | 5 | µA | 2.5 V ≤ VI − VO ≤ 40 V, PD ≤ Pmax; 10 mA ≤ IO ≤ Imax | 3 |
| Reference Voltage | Vref | 1.2 | 1.25 | 1.3 | V | 3.0 V ≤ VI − VO ≤ 40 V, PD ≤ Pmax; 10 mA ≤ IO ≤ Imax | 3 |
| Ripple Rejection (VO = 1.2 V) | RR | 60 | | 80 | dB | VO = 1.2 V, f = 120 Hz | 3 |
| Ripple Rejection (CAdj = 10 µF) | RR | 80 | | | dB | CAdj = 10 µF, VO = 10.0 V, f = 120 Hz | 3 |
| Long Term Stability | S | | 0.3 | 1 | %/1.0k Hrs. | TJ = Thigh; TA = 25°C for endpoint measurements | 3 |
| Temperature Stability | TS | | 0.7 | | % VO | Tlow ≤ TJ ≤ Thigh | 3 |
| Minimum Load Current to Maintain Regulation | ILmin | | 3.5 | 10 | mA | VI − VO = 40 V | 3 |
| RMS Noise | N | | 0.003 | | % VO | TA = 25°C, 10 Hz ≤ f ≤ 10 kHz | 3 |
| Thermal Shutdown | | | 180 | | °C | | 3 |
| Input-Output Voltage Differential | VI−VO | | | 40 | Vdc | | 2 |
| Maximum Junction Temperature | TJMAX | | | 150 | °C | | 2 |
| Storage Temperature Range | Tstg | -65 | | 150 | °C | | 2 |
| Operating Junction Temperature Range (NCV, Tlow to Thigh) | TJ | -40 | | 125 | °C | NCV317LBDR2G SOIC-8 ordering information note: Tlow = −40°C, Thigh = +125°C | 9 |
| Thermal Resistance, Junction-to-Ambient (SOIC-8) | RθJA | | 180 | | °C/W | SOIC-8, minimum recommended pad size (Note 1) | 2 |
| Thermal Resistance, Junction-to-Case (SOIC-8) | RθJC | | 45 | | °C/W | SOIC-8 | 2 |
## CAD (KiCad official)
- Symbol: `NCV317LBDR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ncv317lbdr2g-etched.step` / `ncv317lbdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncv317lbdr2g.step` / `ncv317lbdr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588911018085269504) (11 pp, sha256 `146364af02ceebcc`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncv317lbdr2g-datasheet.pdf)