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NCV308SN330T1G

Public Made by Adom

by adom

onsemi Monitors & Reset Circuits, TSOP-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV308SN330T1G

onsemi · Monitors & Reset Circuits · TSOP-6

NCV308SN330T1G from onsemi, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET output Active-low open-drain N-channel RESET output that is driven low when SENSE is below VIT or MR is low, and needs a pull-up resistor from 10 kΩ to 1 MΩ; RESET pin current is limited to 5 mA maximum.
2 GND power_in Ground terminal that should be connected to the PCB ground reference.
3 MR input Manual Reset input where a logic low asserts RESET; it is internally pulled up to VDD by a 90 kΩ resistor, so it can be left unconnected if unused.
4 CT input Reset delay time setting pin: a 40 kΩ to 200 kΩ resistor to VDD or an open pin gives fixed delays (300 ms or 20 ms), while a ground-referenced capacitor of at least 100 pF gives a programmable 1.25 ms to 10 s delay; CT voltage is limited to −0.3 V to VDD + 0.3 V (≤ 6.0 V).
5 SENSE input Sense input for the monitored voltage, which should be connected directly to that voltage; RESET is asserted when it drops below VIT, and the pin is rated for −0.3 V to +8.0 V.
6 VDD power_in Supply voltage input with an operating range of 1.6 V to 5.5 V, where a 0.1 µF ceramic capacitor placed close to the pin is recommended for transient and parasitic immunity.

Key specifications

Parameter Value
Manufacturer onsemi
Package TSOP-6
Category Power Supply Chip
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Range VDD 1.6 5.5 V −40°C < TJ < +125°C 5
Minimum VDD Guaranteed RESET Output Valid (Note 4) VDD(min) 0.5 0.8 V 5
Low-level output voltage of RESET VOL 0.3 V 1.3V ≤ VDD < 1.6V, IOL = 0.4 mA 5
Low-level output voltage of RESET VOL 0.4 V 1.6V ≤ VDD ≤ 5.5V, IOL = 1.0 mA 5
Negative going SENSE threshold voltage accuracy VIT% -1.75 1.75 % 5
Negative going SENSE threshold voltage accuracy VIT% -0.31 0.31 % TJ = +25°C 5
Negative going SENSE threshold voltage accuracy VIT% -1 1 % −20°C < TJ < +85°C 5
Hysteresis on VIT VHYS 1 3 %VIT 1.6V≤VDD≤4.2V 5
Hysteresis on VIT VHYS 1.75 3.75 %VIT 4.2V≤VDD≤5.5V 5
Supply Current (current into VDD pin) IDD 1.6 5 A VDD = 3.3V, RESET not asserted; MR, RESET, CT open 5
Supply Current (current into VDD pin) IDD 1.6 6 A VDD = 5.5V, RESET not asserted; MR, RESET, CT open 5
Input current at SENSE pin (fixed versions) ISENSE 110 nA Fixed versions VSENSE = 5.5 V 5
RESET leakage current IOH 300 nA VRESET = 5.5 V, RESET not asserted 5
MR logic low input VIL 0 V Printed max is 0.3 VDD 5
Input pulse width to assert RESET (SENSE) tw 20 s SENSE VIH = 1.05 VIT, VIL = 0.95 VIT 5
Input pulse width to assert RESET (MR) tw 150 MR VIH = 0.7 VDD, VIL = 0.3 VDD 5
Propagation delay from MR to RESET tP1 150 ns VIH = 0.7 VDD, VIL = 0.3 VDD 5
Propagation delay from SENSE to RESET tP2 20 s VIH = 1.05 VIT, VIL = 0.95 VIT 5
Internal MR pull-up resistance RMR 90 k 5
Threshold voltage VIT (3.3 V fixed version, NCP308SN330/NCV308SN330) VIT 3.07 V Ordering table: nominal monitored voltage 3.3 V 9
Reset delay time tD 20 ms CT = Open 5
Reset delay time tD 300 ms CT = VDD 5
Reset delay time tD 1.25 ms CT = 100 pF 5
Reset delay time tD 1200 ms CT = 180 nF 5
Input capacitance, CT pin CIN 5 pF CT pin VIN = 0 V to VDD 5
Input capacitance, other pins CIN 5 pF Other pins VIN = 0 V to 5.5 V 5
Input voltage range, VDD VDD -0.3 6 V 4
CT, RESET, MR voltage range VCT, RESET, MR -0.3 6 V Upper limit printed as VDD +0.3, must be ≤ 6.0 4
Current through CT pin ICT 10 mA 4
SENSE pin voltage -0.3 8 V 4
RESET pin current 5 mA 4
Thermal resistance junction-to-air, TSOP-6 RJA 305 °C/W Junction-to-air, TSOP-6 package 4
ESD HBM rating ESD HBM 2000 V Human Body Model, JESD22-A114 (note 1: ±2.0 kV) 4
ESD MM rating ESD MM 100 V Machine Model, JESD22-A115 (note 1: ±100 V) 4
ESD CDM rating ESD CDM 500 V Charged Device Model, JESD22-C101 4
Latch-up current, all pins except digital pins ILU -100 100 mA JESD78 class II, all pins except digital pins 4
Latch-up current, digital pins (MR) ILU -10 10 mA Digital pins (MR) 4
Storage temperature range TSTG -65 150 °C 4
Maximum junction temperature TJ -40 150 °C 4
Operating junction temperature range TJ -40 125 °C Operating temperature range per Table 4 5
RESET pull-up resistor (minimum) 10 k Pull-up from 10k to 1M should be used on RESET 2
RESET pull-up resistor (maximum) 1 M Pull-up from 10k to 1M should be used on RESET 2
CT pin resistor to VDD (fixed delay) 40 200 k CT connected to VDD through resistor, or CT open 2
CT pin capacitor to GND (programmable delay) CT 100 pF Ground-referenced capacitor on CT 2
SENSE bypass capacitor 1 10 nF Bypass capacitor on SENSE input 7

CAD (KiCad official)

  • Symbol: NCV308SN330T1G
  • Footprint: Package_SO:TSOP-6_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-6 (KiCad packages3D, STEP)
  • 3D model files: ncv308sn330t1g-etched.step / ncv308sn330t1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv308sn330t1g.step / ncv308sn330t1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (12 pp, sha256 65285ecc716d91e8, retrieved 2026-10-25, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF