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Contents

README

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NCV20072DR2G

onsemi · Operational Amplifier · SOIC-8

NCV20072DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT 1 output Output of channel 1, which swings rail-to-rail; the maximum output current is ±100 mA, and shorting the output to VDD or VSS adversely affects reliability.
2 IN− 1 input Inverting input of channel 1; the input current must be limited to ±10 mA (series resistors of at least 500 Ω on both inputs may be used).
3 IN+ 1 input Non-inverting input of channel 1; the input common-mode voltage range is VSS to VDD − 1.35 V.
4 VSS power_in Negative supply rail; VDD − VSS must be within 2.7 V to 36 V for single supply or ±1.35 V to ±18 V for split supply.
5 IN+ 2 input Non-inverting input of channel 2; the input common-mode voltage range is VSS to VDD − 1.35 V.
6 IN− 2 input Inverting input of channel 2; the input current must be limited to ±10 mA (series resistors of at least 500 Ω on both inputs may be used).
7 OUT 2 output Output of channel 2, which swings rail-to-rail; the maximum output current is ±100 mA, and shorting the output to VDD or VSS adversely affects reliability.
8 VDD power_in Positive supply rail; VDD − VSS must be within 2.7 V to 36 V for single supply or ±1.35 V to ±18 V for split supply.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS -3 1.3 3 mV VS = 2.7 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply; printed ±3 mV 6
Input Bias Current IIB 5 200 pA VS = 2.7 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 6
Input Offset Current (NCx20071, NCx20072) IOS 2 75 pA VS = 2.7 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 6
Channel Separation XTLK 100 dB DC; NCx20072 6
Common Mode Rejection Ratio CMRR 90 110 dB VS = 2.7 V; VCM = VSS + 0.2 V to VDD − 1.35 V 6
Open Loop Voltage Gain AVOL 96 118 dB VS = 2.7 V; TA = 25°C; RL ≥ 10 k 6
Output Current Capability, op amp sinking current IO 70 mA VS = 2.7 V; op amp sinking current 6
Output Current Capability, op amp sourcing current IO 50 mA VS = 2.7 V; op amp sourcing current 6
Output Voltage High VOH 0.006 0.15 V VS = 2.7 V; voltage output swing from positive rail 6
Output Voltage Low VOL 0.005 0.15 V VS = 2.7 V; voltage output swing from negative rail 6
Power Supply Rejection Ratio PSRR 114 135 dB VS = 2.7 V; no load 7
Power Supply Quiescent Current (per channel) IDD 405 525 A VS = 2.7 V; per channel, no load 7
Input Offset Voltage VOS -3 1.3 3 mV VS = 5 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply; printed ±3 mV 7
Input Bias Current IIB 5 200 pA VS = 5 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 7
Input Offset Current (NCx20071, NCx20072) IOS 2 75 pA VS = 5 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 7
Common Mode Rejection Ratio CMRR 102 125 dB VS = 5 V; VCM = VSS + 0.2 V to VDD − 1.35 V 8
Open Loop Voltage Gain AVOL 96 120 dB VS = 5 V; TA = 25°C; RL ≥ 10 k 8
Output Current Capability, op amp sinking current IO 50 mA VS = 5 V; op amp sinking current 8
Output Current Capability, op amp sourcing current IO 60 mA VS = 5 V; op amp sourcing current 8
Output Voltage High VOH 0.013 0.2 V VS = 5 V; voltage output swing from positive rail 8
Output Voltage Low VOL 0.01 0.1 V VS = 5 V; voltage output swing from negative rail 8
Power Supply Rejection Ratio PSRR 114 135 dB VS = 5 V; no load 8
Power Supply Quiescent Current (per channel) IDD 410 530 A VS = 5 V; per channel, no load 8
Input Offset Voltage VOS -3 1.3 3 mV VS = 10 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply; printed ±3 mV 9
Input Bias Current IIB 5 200 pA VS = 10 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 9
Input Offset Current (NCx20071, NCx20072) IOS 2 75 pA VS = 10 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 9
Common Mode Rejection Ratio CMRR 110 130 dB VS = 10 V; VCM = VSS + 0.2 V to VDD − 1.35 V 9
Open Loop Voltage Gain AVOL 98 120 dB VS = 10 V; TA = 25°C; RL ≥ 10 k 9
Output Current Capability, op amp sinking current IO 50 mA VS = 10 V; op amp sinking current 9
Output Current Capability, op amp sourcing current IO 65 mA VS = 10 V; op amp sourcing current 9
Output Voltage High VOH 0.023 0.08 V VS = 10 V; voltage output swing from positive rail 9
Output Voltage Low VOL 0.022 0.3 V VS = 10 V; voltage output swing from negative rail 9
Power Supply Rejection Ratio PSRR 114 135 dB VS = 10 V; no load 10
Power Supply Quiescent Current (per channel) IDD 416 540 A VS = 10 V; per channel, no load 10
Input Offset Voltage VOS -3 1.3 3 mV VS = 36 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply; printed ±3 mV 10
Input Bias Current IIB 5 200 pA VS = 36 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 10
Input Offset Current (NCx20071, NCx20072) IOS 2 75 pA VS = 36 V; TA = 25°C; RL ≥ 10 k; VCM = VOUT = mid−supply 10
Common Mode Rejection Ratio (NCx20072) CMRR 120 145 dB VS = 36 V; VCM = VSS + 0.2 V to VDD − 1.35 V 11
Open Loop Voltage Gain AVOL 98 120 dB VS = 36 V; TA = 25°C; RL ≥ 10 k 11
Output Current Capability, op amp sinking current IO 50 mA VS = 36 V; op amp sinking current 11
Output Current Capability, op amp sourcing current IO 65 mA VS = 36 V; op amp sourcing current 11
Output Voltage High (NCx20072) VOH 0.074 0.1 V VS = 36 V; voltage output swing from positive rail 11
Output Voltage Low VOL 0.065 0.3 V VS = 36 V; voltage output swing from negative rail 11
Power Supply Rejection Ratio PSRR 114 135 dB VS = 36 V; no load 12
Power Supply Quiescent Current (per channel) IDD 465 570 A VS = 36 V; per channel, no load 12
Supply Voltage (VDD − VSS) VS 40 V Absolute maximum supply voltage 5
Maximum Input Current IIN -10 10 mA Maximum input current 5
Maximum Output Current IO -100 100 mA Maximum output current 5
Continuous Total Power Dissipation PD 200 mW Continuous total power dissipation 5
Maximum Junction Temperature TJ 150 °C Maximum junction temperature 5
Storage Temperature Range TSTG -65 150 °C Storage temperature range 5
ESD Human Body Model HBM 2000 V JEDEC JS-001 (AEC-Q100-002) 5
ESD Machine Model MM 150 V JESD22-A115; NCx20072, NCx20074 5
ESD Charged Device Model CDM 2000 V JESD22-C101; NCx20071, NCx20072; (C6) 5
Latch-Up Current ILU 100 mA JESD78 (AEC-Q100-004) 5
Operating Supply Voltage (Single Supply) VS 2.7 36 V Single supply 5
Operating Supply Voltage (Split Supply) VS 1.35 18 V Split supply; printed ±1.35 V to ±18 V 5
Ambient Temperature TA -40 125 °C Operating ambient temperature 5
Junction-to-Ambient Thermal Resistance, SOIC-8 JA 190 °C/W Single layer board (1S, JEDEC51-3) 5
Junction-to-Ambient Thermal Resistance, SOIC-8 JA 131 °C/W Multi-layer board (1S2P, JEDEC51-7) 5

CAD (KiCad official)

  • Symbol: NCV20072DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncv20072dr2g-etched.step / ncv20072dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv20072dr2g.step / ncv20072dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (25 pp, sha256 dcd388200559389e, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF