component
NCV1034DR2G
Public Made by Adomby adom
onsemi AC-DC Controllers & Regulators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NCV1034DR2G
onsemi · AC-DC Controllers & Regulators · SOIC-16
NCV1034DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OCset | input | Current limit set point; a resistor from this pin to GND sets the positive and negative current limit threshold (abs max -0.3 to 10 V). |
| 2 | FB | input | Inverting input to the error amplifier, connected to the regulator output via a resistor divider to set the output voltage (abs max -0.3 to 10 V). |
| 3 | COMP | output | Error amplifier output, typically with an external resistor and capacitor network to ground for loop compensation (abs max -0.3 to 5 V). |
| 4 | SS/SD | input | Soft-start/shutdown pin; an external capacitor to ground sets the startup time and pulling the pin below 0.3 V shuts down the converter. |
| 5 | SYNC | bidirectional | Synchronizes the internal oscillator to an external clock or outputs sync to other ICs; if unused, connect via a 10 k resistor to ground. |
| 6 | PGND | power_in | Power ground for the MOSFET driver, to be connected to the system's power ground plane. |
| 7 | LDRV | output | Output driver for the low side MOSFET (abs max -0.3 to VCC + 0.3 V). |
| 8 | DRVVCC | power_in | Bias supply for the internal low side driver, 10 to 18 V recommended, with a minimum 0.1 uF high frequency capacitor to power ground. |
| 9 | VB | power_in | High side driver supply that must be connected to a voltage higher than input voltage, with a minimum 0.1 uF capacitor to the switch node; VB to VS 10 to 18 V. |
| 10 | HDRV | output | Output driver for the high side MOSFET (abs max VS - 0.3 to VB + 0.3 V). |
| 11 | VS | power_in | Switch node connected to the source of the upper MOSFET and drain of the lower MOSFET, and return path for the upper gate driver (abs max -1.0 to 150 V). |
| 12 | VCC | power_in | Power supply for the internal IC blocks, 10 to 18 V recommended, with a minimum 0.1 uF high frequency capacitor to ground. |
| 13 | OCIN | input | Overcurrent sensing input; a series resistor to the drain of the low side MOSFET must limit the current into this pin (20 mA max input current). |
| 14 | GND | power_in | Signal ground for internal reference and control circuitry. |
| 15 | RT | passive | A resistor from this pin to ground sets the oscillator frequency (25 to 500 kHz operating). |
| 16 | UVLO | input | An external voltage divider on this pin sets the undervoltage threshold levels (abs max -0.3 to 10 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Power Supply Chip |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Voltage | VFB | 1.214 | 1.25 | 1.289 | V | VCC = 12 V, DRVVCC = VB = 12 V, -40C < TJ < 125C | 6 |
| VCC Supply Current (Static) | ICC(Static) | 2 | 3 | mA | SS = 0 V, No Switching, RT = 10 k, ROCSET = 10 k | 6 | |
| DRVVCC Supply Current (Static) | IC(Static) | 0.1 | 0.3 | mA | SS = 0 V, No Switching | 6 | |
| VB Supply Current (Static) | IB(Static) | 0.1 | 0.3 | mA | SS = 0 V, No Switching | 6 | |
| VCC Start Threshold | VCC_UVLO (R) | 7.9 | 8.9 | 9.8 | V | Supply Ramping Up | 6 |
| VCC Stop Threshold | VCC_UVLO (F) | 7.3 | 8.2 | 9 | V | Supply Ramping Down | 6 |
| DRVCC Start Threshold | DRVCC_UVLO (R) | 7.9 | 8.9 | 9.8 | V | Supply Ramping Up | 6 |
| DRVCC Stop Threshold | DRVCC_UVLO (F) | 7.3 | 8.2 | 9 | V | Supply Ramping Down | 6 |
| VB Start Threshold | VB_UVLO (R) | 7.9 | 8.9 | 9.8 | V | Supply Ramping Up | 6 |
| VB Stop Threshold | VB_UVLO (F) | 7.3 | 8.2 | 9 | V | Supply Ramping Down | 6 |
| Undervoltage Threshold Value (Rising) | UUVLO (Rising) | 1.18 | 1.25 | 1.31 | V | 6 | |
| Undervoltage Threshold Value (Falling) | UUVLO (Falling) | 1.09 | 1.15 | 1.2 | V | 6 | |
| Oscillator Frequency | FS | 170 | 200 | 230 | kHz | RT = 20 k | 6 |
| Oscillator Frequency | FS | 320 | 375 | 430 | kHz | RT = 10 k | 6 |
| Dead Band Time | tdead | 30 | 60 | 120 | ns | (See Figure 3) | 7 |
| Soft-Start Current | ISS | 15 | 20 | 25 | A | SS = 0 V | 7 |
| Error Amp Source/Sink Current | I(Source/Sink) | 50 | 100 | 120 | A | 7 | |
| Error Amp Transconductance | gm | 1500 | 3150 | 4000 | mho | (Note 4) | 7 |
| LO Output Resistor, Source | RLOH | 7 | 12 | Ω | Typical Value @ 25C, (Note 4) | 7 | |
| LO Output Resistor, Sink | RLOL | 2 | 8 | Ω | Typical Value @ 25C, (Note 4) | 7 | |
| HI Output Resistor, Source | RHIH | 7 | 12 | Ω | Typical Value @ 25C, (Note 4) | 7 | |
| HI Output Resistor, Sink | RHIL | 2 | 8 | Ω | Typical Value @ 25C, (Note 4) | 7 | |
| Shutdown Output Threshold | SD | 0.3 | 0.4 | V | 7 | ||
| Supply Voltage VCC | VCC | 10 | 18 | V | 5 | ||
| Supply Voltage DRVCC | DRVCC | 10 | 18 | V | 5 | ||
| VB to VS Supply Voltage | VB to VS | 10 | 18 | V | 5 | ||
| Converting Voltage | VIN | 100 | V | 5 | |||
| Operating Frequency | FSW | 25 | 500 | kHz | 5 | ||
| Junction Temperature | TJ | -40 | 125 | C | 5 | ||
| FB, VUVLO, RT, OCset | -0.3 | 10 | V | Referenced to GND | 5 | ||
| COMP, SS/SD, SYNC, OCIN | -0.3 | 5 | V | Referenced to GND | 5 | ||
| DRVVCC, VCC | -0.3 | 20 | V | Referenced to GND | 5 | ||
| VS | VS | -1 | 150 | V | Referenced to GND | 5 | |
| OCin Input Current | 20 | mA | 5 | ||||
| Thermal Resistance, Junction-to-Ambient | RθJA | 130 | C/W | 5 | |||
| Operating Ambient Temperature Range | TA | -40 | 125 | C | 5 | ||
| Storage Temperature Range | TSTG | -55 | 150 | C | 5 | ||
| Junction Operating Temperature | TJ | -40 | 150 | C | 5 | ||
| ESD Withstand Voltage HBM (Note 1) | VESD | 2000 | V | Excluding pins Vb, VS and HDRV | 5 | ||
| ESD Withstand Voltage HBM (Note 2) | VESD | 1000 | V | Includes all pins | 5 | ||
| ESD Withstand Voltage CDM | VESD | 500 | V | 5 |
CAD (KiCad official)
- Symbol:
NCV1034DR2G - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ncv1034dr2g-etched.step/ncv1034dr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncv1034dr2g.step/ncv1034dr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (27 pp, sha256
d2452ae484389fa2, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NCV1034DR2G
**onsemi** · AC-DC Controllers & Regulators · SOIC-16
NCV1034DR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OCset | input | Current limit set point; a resistor from this pin to GND sets the positive and negative current limit threshold (abs max -0.3 to 10 V). |
| 2 | FB | input | Inverting input to the error amplifier, connected to the regulator output via a resistor divider to set the output voltage (abs max -0.3 to 10 V). |
| 3 | COMP | output | Error amplifier output, typically with an external resistor and capacitor network to ground for loop compensation (abs max -0.3 to 5 V). |
| 4 | SS/SD | input | Soft-start/shutdown pin; an external capacitor to ground sets the startup time and pulling the pin below 0.3 V shuts down the converter. |
| 5 | SYNC | bidirectional | Synchronizes the internal oscillator to an external clock or outputs sync to other ICs; if unused, connect via a 10 k resistor to ground. |
| 6 | PGND | power_in | Power ground for the MOSFET driver, to be connected to the system's power ground plane. |
| 7 | LDRV | output | Output driver for the low side MOSFET (abs max -0.3 to VCC + 0.3 V). |
| 8 | DRVVCC | power_in | Bias supply for the internal low side driver, 10 to 18 V recommended, with a minimum 0.1 uF high frequency capacitor to power ground. |
| 9 | VB | power_in | High side driver supply that must be connected to a voltage higher than input voltage, with a minimum 0.1 uF capacitor to the switch node; VB to VS 10 to 18 V. |
| 10 | HDRV | output | Output driver for the high side MOSFET (abs max VS - 0.3 to VB + 0.3 V). |
| 11 | VS | power_in | Switch node connected to the source of the upper MOSFET and drain of the lower MOSFET, and return path for the upper gate driver (abs max -1.0 to 150 V). |
| 12 | VCC | power_in | Power supply for the internal IC blocks, 10 to 18 V recommended, with a minimum 0.1 uF high frequency capacitor to ground. |
| 13 | OCIN | input | Overcurrent sensing input; a series resistor to the drain of the low side MOSFET must limit the current into this pin (20 mA max input current). |
| 14 | GND | power_in | Signal ground for internal reference and control circuitry. |
| 15 | RT | passive | A resistor from this pin to ground sets the oscillator frequency (25 to 500 kHz operating). |
| 16 | UVLO | input | An external voltage divider on this pin sets the undervoltage threshold levels (abs max -0.3 to 10 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-16 |
| Category | Power Supply Chip |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Voltage | VFB | 1.214 | 1.25 | 1.289 | V | VCC = 12 V, DRVVCC = VB = 12 V, -40C < TJ < 125C | 6 |
| VCC Supply Current (Static) | ICC(Static) | | 2 | 3 | mA | SS = 0 V, No Switching, RT = 10 k, ROCSET = 10 k | 6 |
| DRVVCC Supply Current (Static) | IC(Static) | | 0.1 | 0.3 | mA | SS = 0 V, No Switching | 6 |
| VB Supply Current (Static) | IB(Static) | | 0.1 | 0.3 | mA | SS = 0 V, No Switching | 6 |
| VCC Start Threshold | VCC_UVLO (R) | 7.9 | 8.9 | 9.8 | V | Supply Ramping Up | 6 |
| VCC Stop Threshold | VCC_UVLO (F) | 7.3 | 8.2 | 9 | V | Supply Ramping Down | 6 |
| DRVCC Start Threshold | DRVCC_UVLO (R) | 7.9 | 8.9 | 9.8 | V | Supply Ramping Up | 6 |
| DRVCC Stop Threshold | DRVCC_UVLO (F) | 7.3 | 8.2 | 9 | V | Supply Ramping Down | 6 |
| VB Start Threshold | VB_UVLO (R) | 7.9 | 8.9 | 9.8 | V | Supply Ramping Up | 6 |
| VB Stop Threshold | VB_UVLO (F) | 7.3 | 8.2 | 9 | V | Supply Ramping Down | 6 |
| Undervoltage Threshold Value (Rising) | UUVLO (Rising) | 1.18 | 1.25 | 1.31 | V | | 6 |
| Undervoltage Threshold Value (Falling) | UUVLO (Falling) | 1.09 | 1.15 | 1.2 | V | | 6 |
| Oscillator Frequency | FS | 170 | 200 | 230 | kHz | RT = 20 k | 6 |
| Oscillator Frequency | FS | 320 | 375 | 430 | kHz | RT = 10 k | 6 |
| Dead Band Time | tdead | 30 | 60 | 120 | ns | (See Figure 3) | 7 |
| Soft-Start Current | ISS | 15 | 20 | 25 | A | SS = 0 V | 7 |
| Error Amp Source/Sink Current | I(Source/Sink) | 50 | 100 | 120 | A | | 7 |
| Error Amp Transconductance | gm | 1500 | 3150 | 4000 | mho | (Note 4) | 7 |
| LO Output Resistor, Source | RLOH | | 7 | 12 | Ω | Typical Value @ 25C, (Note 4) | 7 |
| LO Output Resistor, Sink | RLOL | | 2 | 8 | Ω | Typical Value @ 25C, (Note 4) | 7 |
| HI Output Resistor, Source | RHIH | | 7 | 12 | Ω | Typical Value @ 25C, (Note 4) | 7 |
| HI Output Resistor, Sink | RHIL | | 2 | 8 | Ω | Typical Value @ 25C, (Note 4) | 7 |
| Shutdown Output Threshold | SD | | 0.3 | 0.4 | V | | 7 |
| Supply Voltage VCC | VCC | 10 | | 18 | V | | 5 |
| Supply Voltage DRVCC | DRVCC | 10 | | 18 | V | | 5 |
| VB to VS Supply Voltage | VB to VS | 10 | | 18 | V | | 5 |
| Converting Voltage | VIN | | | 100 | V | | 5 |
| Operating Frequency | FSW | 25 | | 500 | kHz | | 5 |
| Junction Temperature | TJ | -40 | | 125 | C | | 5 |
| FB, VUVLO, RT, OCset | | -0.3 | | 10 | V | Referenced to GND | 5 |
| COMP, SS/SD, SYNC, OCIN | | -0.3 | | 5 | V | Referenced to GND | 5 |
| DRVVCC, VCC | | -0.3 | | 20 | V | Referenced to GND | 5 |
| VS | VS | -1 | | 150 | V | Referenced to GND | 5 |
| OCin Input Current | | | | 20 | mA | | 5 |
| Thermal Resistance, Junction-to-Ambient | RθJA | | 130 | | C/W | | 5 |
| Operating Ambient Temperature Range | TA | -40 | | 125 | C | | 5 |
| Storage Temperature Range | TSTG | -55 | | 150 | C | | 5 |
| Junction Operating Temperature | TJ | -40 | | 150 | C | | 5 |
| ESD Withstand Voltage HBM (Note 1) | VESD | | | 2000 | V | Excluding pins Vb, VS and HDRV | 5 |
| ESD Withstand Voltage HBM (Note 2) | VESD | | | 1000 | V | Includes all pins | 5 |
| ESD Withstand Voltage CDM | VESD | | | 500 | V | | 5 |
## CAD (KiCad official)
- Symbol: `NCV1034DR2G`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `ncv1034dr2g-etched.step` / `ncv1034dr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ncv1034dr2g.step` / `ncv1034dr2g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://www.onsemi.com/pdf/datasheet/ncv1034-d.pdf) (27 pp, sha256 `d2452ae484389fa2`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ncv1034dr2g-datasheet.pdf)