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Contents

README

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NCS20062DR2G

onsemi · Operational Amplifier · SOIC-8

NCS20062DR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT 1 output Channel 1 output, rail-to-rail; output voltage high/low are typically 3 mV from the rails at 1.8 V (19 mV max), with short-circuit current of 19 mA sinking and 15 mA sourcing and an absolute maximum output current of ±100 mA.
2 IN− 1 input Channel 1 inverting input; common-mode range is VSS − 0.2 V to VDD + 0.2 V, absolute input voltage is VSS − 0.5 V to VDD + 0.5 V, and maximum input current is ±10 mA.
3 IN+ 1 input Channel 1 non-inverting input; common-mode range is VSS − 0.2 V to VDD + 0.2 V, absolute input voltage is VSS − 0.5 V to VDD + 0.5 V, and maximum input current is ±10 mA.
4 VSS power_in Negative supply rail; operating supply voltage (VDD − VSS) is 1.8 V to 5.5 V and the absolute maximum supply voltage is 7 V.
5 IN+ 2 input Channel 2 non-inverting input; common-mode range is VSS − 0.2 V to VDD + 0.2 V, absolute input voltage is VSS − 0.5 V to VDD + 0.5 V, and maximum input current is ±10 mA.
6 IN− 2 input Channel 2 inverting input; common-mode range is VSS − 0.2 V to VDD + 0.2 V, absolute input voltage is VSS − 0.5 V to VDD + 0.5 V, and maximum input current is ±10 mA.
7 OUT 2 output Channel 2 output, rail-to-rail; short-circuit current is 19 mA sinking and 15 mA sourcing at 1.8 V, and absolute maximum output current is ±100 mA.
8 VDD power_in Positive supply rail; operating supply voltage is 1.8 V to 5.5 V with an absolute maximum of 7 V, and quiescent current is 125 µA typical per channel with no load.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Amplifiers/Comparators
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input Offset Voltage VOS 0.5 3.5 mV VS = 1.8 V; TA = 25°C 5
Input Offset Voltage VOS 4 mV VS = 1.8 V; over TA −40°C to 125°C 5
Input Bias Current IIB 1 1500 pA VS = 1.8 V; max over TA −40°C to 125°C 5
Input Offset Current IOS 1 1100 pA VS = 1.8 V; max over TA −40°C to 125°C 5
Common Mode Rejection Ratio CMRR 48 73 dB VS = 1.8 V; VCM = VSS, 0.2 to VDD + 0.2 5
Common Mode Rejection Ratio CMRR 45 dB VS = 1.8 V; VCM = VSS + 0.2 to VDD − 0.2 5
Open Loop Voltage Gain AVOL 86 120 dB VS = 1.8 V; TA = 25°C 5
Open Loop Voltage Gain AVOL 80 dB VS = 1.8 V; over TA −40°C to 125°C 5
Output Voltage High VOH 3 19 mV VS = 1.8 V; voltage output swing from positive rail 5
Output Voltage High VOH 20 mV VS = 1.8 V; over TA −40°C to 125°C 5
Output Voltage Low VOL 3 19 mV VS = 1.8 V; voltage output swing from negative rail 5
Output Voltage Low VOL 20 mV VS = 1.8 V; over TA −40°C to 125°C 5
Power Supply Rejection Ratio PSRR 67 90 dB VS = 1.8 V; no load; TA = 25°C 5
Power Supply Rejection Ratio PSRR 64 dB VS = 1.8 V; no load; over TA −40°C to 125°C 5
Power Supply Quiescent Current IDD 125 170 µA VS = 1.8 V; per channel, no load 5
Input Offset Voltage VOS 0.5 3.5 mV VS = 3.3 V; TA = 25°C 6
Input Offset Voltage VOS 4 mV VS = 3.3 V; over TA −40°C to 125°C 6
Input Bias Current IIB 1 1500 pA VS = 3.3 V; max over TA −40°C to 125°C 6
Input Offset Current IOS 1 1100 pA VS = 3.3 V; max over TA −40°C to 125°C 6
Common Mode Rejection Ratio CMRR 53 76 dB VS = 3.3 V; VCM = VSS, 0.2 to VDD + 0.2 6
Common Mode Rejection Ratio CMRR 48 dB VS = 3.3 V; VCM = VSS + 0.2 to VDD − 0.2 6
Open Loop Voltage Gain AVOL 90 120 dB VS = 3.3 V; TA = 25°C 6
Open Loop Voltage Gain AVOL 86 dB VS = 3.3 V; over TA −40°C to 125°C 6
Output Voltage High VOH 3 24 mV VS = 3.3 V; voltage output swing from positive rail 6
Output Voltage High VOH 25 mV VS = 3.3 V; over TA −40°C to 125°C 6
Output Voltage Low VOL 3 24 mV VS = 3.3 V; voltage output swing from negative rail 6
Output Voltage Low VOL 25 mV VS = 3.3 V; over TA −40°C to 125°C 6
Power Supply Rejection Ratio PSRR 67 90 dB VS = 3.3 V; no load; TA = 25°C 6
Power Supply Rejection Ratio PSRR 64 dB VS = 3.3 V; no load; over TA −40°C to 125°C 6
Power Supply Quiescent Current IDD 135 180 µA VS = 3.3 V; per channel, no load 6
Input Offset Voltage VOS 0.5 3.5 mV VS = 5.5 V; TA = 25°C 7
Input Offset Voltage VOS 4 mV VS = 5.5 V; over TA −40°C to 125°C 7
Input Bias Current IIB 1 1500 pA VS = 5.5 V; max over TA −40°C to 125°C 7
Input Offset Current IOS 1 1100 pA VS = 5.5 V; max over TA −40°C to 125°C 7
Common Mode Rejection Ratio CMRR 55 79 dB VS = 5.5 V; VCM = VSS, 0.2 to VDD + 0.2 7
Common Mode Rejection Ratio CMRR 51 dB VS = 5.5 V; VCM = VSS + 0.2 to VDD − 0.2 7
Open Loop Voltage Gain AVOL 90 120 dB VS = 5.5 V; TA = 25°C 7
Open Loop Voltage Gain AVOL 86 dB VS = 5.5 V; over TA −40°C to 125°C 7
Output Voltage High VOH 3 24 mV VS = 5.5 V; voltage output swing from positive rail 7
Output Voltage High VOH 25 mV VS = 5.5 V; over TA −40°C to 125°C 7
Output Voltage Low VOL 3 24 mV VS = 5.5 V; voltage output swing from negative rail 7
Output Voltage Low VOL 25 mV VS = 5.5 V; over TA −40°C to 125°C 7
Power Supply Rejection Ratio PSRR 67 90 dB VS = 5.5 V; no load; TA = 25°C 7
Power Supply Rejection Ratio PSRR 64 dB VS = 5.5 V; no load; over TA −40°C to 125°C 7
Power Supply Quiescent Current IDD 140 200 µA VS = 5.5 V; per channel, no load 7
Supply Voltage (VDD − VSS) VS 7 V Note 2 4
Maximum Input Current II -10 10 mA 4
Maximum Output Current IO -100 100 mA 4
Continuous Total Power Dissipation PD 200 mW Note 2 4
Maximum Junction Temperature TJ 150 °C 4
Storage Temperature Range TSTG -65 150 °C 4
Mounting Temperature Tmount 260 °C Infrared or convection, 20 sec 4
ESD Capability Human Body Model ESDHBM 2000 V Human Body Model 4
ESD Capability Machine Model ESDMM 100 V Machine Model 4
ESD Capability Charge Device Model ESDCDM 2000 V Charge Device Model 4
Latch-Up Current ILU 100 mA JESD78 4
Operating Supply Voltage VS 1.8 5.5 V 4
Ambient Temperature TA -40 125 °C 4
Junction to Ambient Thermal Resistance (SOIC-8, Dual) JA 190 °C/W Single layer board (Note 6) 4
Junction to Ambient Thermal Resistance (SOIC-8, Dual) JA 131 °C/W Multi-layer board (Note 7) 4

CAD (KiCad official)

  • Symbol: NCS20062DR2G
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ncs20062dr2g-etched.step / ncs20062dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncs20062dr2g.step / ncs20062dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (20 pp, sha256 d7419cc9b429e894, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF