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NCP81610AMNTXG

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onsemi AC-DC Controllers And Regulators, QFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCP81610AMNTXG

onsemi · AC-DC Controllers And Regulators · QFN-40(5x5)

NCP81610AMNTXG from onsemi, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REFIN input Reference voltage input for output voltage regulation, set by the PWM_VID interface.
2 VREF power_in 2.0 V reference voltage output; a 10 nF ceramic capacitor is required from this pin to ground.
3 VRMP input Feed-forward input of VIN for ramp slope compensation; rising UVLO threshold is 2.8 V.
4 PWM8/SS bidirectional PWM 8 output and soft-start setting; during startup a resistor to ground programs the soft-start time.
5 PWM7/I2C bidirectional PWM 7 output and I2C address; during startup a resistor to ground programs the I2C address.
6 PWM6/LPC1 bidirectional PWM 6 output and low phase count 1; during startup a resistor to ground programs the warm boot-up power zone (PSI set low).
7 PWM5/LPC2 bidirectional PWM 5 output and low phase count 2; during startup a resistor to ground programs the cold boot-up power zone (PSI set low).
8 PWM4/PHTH1 bidirectional PWM 4 output and phase shedding threshold 1; during startup a resistor to ground programs the threshold (PSI set to mid state).
9 PWM3/PHTH2 bidirectional PWM 3 output and phase shedding threshold 2; during startup a resistor to ground programs the threshold (PSI set to mid state).
10 PWM2/PHTH3 bidirectional PWM 2 output and phase shedding threshold 3; during startup a resistor to ground programs the threshold (PSI set to mid state).
11 PWM1/PHTH4 bidirectional PWM 1 output and phase shedding threshold 4; during startup a resistor to ground programs the threshold (PSI set to mid state).
12 DRON bidirectional Bidirectional gate driver enable for external drivers.
13 CSP8 input Non-inverting input to current balance sense amplifier for phase 8; a pull-up to VCC with a 2 k resistor disables the PWM8 output.
14 CSP7 input Non-inverting input to current balance sense amplifier for phase 7; a pull-up to VCC with a 2 k resistor disables the PWM7 output.
15 CSP6 input Non-inverting input to current balance sense amplifier for phase 6; a pull-up to VCC with a 2 k resistor disables the PWM6 output.
16 CSP5 input Non-inverting input to current balance sense amplifier for phase 5; a pull-up to VCC with a 2 k resistor disables the PWM5 output.
17 CSP4 input Non-inverting input to current balance sense amplifier for phase 4; a pull-up to VCC with a 2 k resistor disables the PWM4 output.
18 CSP3 input Non-inverting input to current balance sense amplifier for phase 3; a pull-up to VCC with a 2 k resistor disables the PWM3 output.
19 CSP2 input Non-inverting input to current balance sense amplifier for phase 2; a pull-up to VCC with a 2 k resistor disables the PWM2 output.
20 CSP1 input Non-inverting input to current balance sense amplifier for phase 1; a pull-up to VCC with a 2 k resistor disables the PWM1 output.
21 CSREF input Total output current sense amplifier reference voltage input.
22 CSSUM input Inverting input of the total current sense amplifier.
23 CSCOMP output Output of the total current sense amplifier.
24 ILIM bidirectional Over current limit (OCL) threshold setting input; the threshold is set by a shunt resistor to ground.
25 IOUT output Total output current; a resistor to GND is required to give a 2 V drop at the maximum output current.
26 TMON input DRMOS temperature monitoring input; linear range 0.6 V to 1.9 V with default latch threshold 2.0 V.
27 FSW input A resistor to ground from this pin sets the regulator operating frequency.
28 DIFF output Output of the regulator's differential remote sense amplifier.
29 FB input Error amplifier inverting (feedback) input.
30 COMP output Output of the error amplifier and the inverting input of the PWM comparator.
31 VSP input Differential output voltage sense positive terminal.
32 VSN input Differential output voltage sense negative terminal.
33 VCC power_in Power for the internal control circuits (4.6 V to 5.4 V supply); a 1 µF decoupling capacitor is required from this pin to ground.
34 SDA bidirectional Serial data bi-directional pin; requires a pull-up resistor to VCC.
35 SCL input Serial bus clock pin; requires a pull-up resistor to VCC.
36 EN input Logic input: logic high enables the regulator output, logic low disables the regulator output.
37 PSI input Power Saving Interface control pin; can be set low, high or left floating.
38 PGOOD output Open-drain power good indicator output.
39 PWM_VID input PWM_VID buffer input.
40 VID_BUFF output PWM_VID pulse output from the internal buffer.
41 AGND power_in Analog ground and thermal pad, connected to system ground.

Key specifications

Parameter Value
Manufacturer onsemi
Package QFN-40(5x5)
Category Power Management (PMIC)
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VSN Pin Voltage Range (relative to GND) VSN -0.3 0.3 V Relative to GND (printed GND−0.3 to GND+0.3) 5
VCC Pin Voltage VCC -0.3 6.5 V 5
VRMP Pin Voltage VRMP -0.3 25 V 5
PWM_VID Pin Voltage PWM_VID -0.3 V Min −2 V for <50 ns; max printed as VCC+0.3 V 5
All Other Pins Voltage -0.3 V Max printed as VCC+0.3 V 5
COMP Pin Current Range -2 2 mA 5
CSCOMP, DIFF, PGOOD, VSN Pin Current -1 1 mA 5
VCC Supply Voltage Range 4.6 5.4 V 6
VCC Quiescent Current ICC 100 µA Enable low, 2nd time 6
UVLO Threshold Rising UVLORise 4.5 V VCC Rising 6
UVLO Threshold Falling UVLOFall 4 V VCC Falling 6
Switching Frequency Range FSW 250 1200 kHz 8 phase configuration 6
Switching Frequency Accuracy FSW -4 4 % FSW = 810 kHz 6
EN Upper Threshold VIH 1.2 V 6
EN Lower Threshold VIL 0.6 V 6
DRON Output High Voltage VOH 3 V Sourcing 500 µA 6
DRON Output Low Voltage VOL 0.1 V Sinking 500 µA 6
PGOOD Output Low Voltage VOL 0.4 V IPGOOD = 10 mA (sink) 6
Output Voltage Initialization Time T_init 0.5 ms From EN to ramp starts, 2nd ENABLE 6
Total Soft Startup Period T_total 2 ms T_Ramp ≤ 0101, RT_Ramp ≤ 41.2 k; From EN to PGOOD 6
VRMP Supply Range VRMP 2.8 20 V 6
VRMP Falling UVLO VRMPfall 2.5 V VRMP falling 6
Under Voltage Protection (UVP) Threshold UVP -400 mV Relative to REFIN Voltage 6
Over Voltage Protection (OVP) Threshold OVP 500 mV Relative to REFIN Voltage 6
TMON External Temperature Monitoring Linear Range TMON 0.6 1.9 V 6
TMON Latch Threshold Default TMONLT 1.9 2 2.1 V Default 6
TMON Linear Range (TMONLN) TMONLN 0 2 V 7
Chip Thermal Shutdown Temperature TSD 145 155 °C Temperature Rising 7
ILIM Sourcing Current ILIM 9 10 11 µA 7
ILIM Range VILIM 0 2 V 7
RILIM Range RILIM 0 200 kΩ 7
PWM Output High Voltage (relative to VCC) VOH -0.2 V Sourcing 500 µA; printed as VCC−0.2 V, value is offset from VCC 7
PWM Output Mid Voltage VMID 1.4 1.5 1.6 V 7
PWM Output Low Voltage VOL 0.6 V Sinking 500 µA 7
PWM Phase Angle Error ∅ -15 15 ° Between adjacent phases 7
Phase Detection Threshold Voltage (relative to VCC) VPHDET -0.1 V CSP2 to CSP8; printed as VCC−0.1 V, value is offset from VCC 7
Error Amplifier Maximum Output Voltage VOUT 3.5 V ISOURCE = 2mA 7
Error Amplifier Minimum Output Voltage VOUT 1 V ISINK = 2mA 7
VSP Input Voltage VIN 0 2 V 7
Differential Summing Amplifier Maximum Output Voltage VOUT 3 V ISOURCE = 2 mA 7
Differential Summing Amplifier Minimum Output Voltage VOUT 0.8 V ISINK = 2 mA 7
PSI High Threshold VIH 1.45 V 8
PSI Mid Threshold VMID 0.8 1 V Auto Phase Shedding Enabled 9
PSI Low Threshold VIL 0.575 V 9
VREF Reference Voltage VREF 1.98 2 2.02 V IREF = 1 mA 8
VREF Reference Accuracy VREF 1 1.5 % Over Temp 8
PWM_VID Buffer Upper Threshold VIH 1.4 V 8
PWM_VID Buffer Lower Threshold VIL 0.5 V 8
PWM_VID Switching Frequency FPWM_VID 400 5000 kHz 8
VOCL_min Voltage Range VOCL_min 0.2 1.3 V 8
I2C Logic High Input Voltage VIH 1.4 5 V 9
I2C Logic Low Input Voltage VIL 0 0.5 V 9
I2C Output Low Voltage VOL 0.4 V ISDA = −6 mA 9
I2C Clock Frequency fSCL 400 kHz see Figure 2 9
Current Sense Amplifier Gain G 5.5 6 6.5 V/V −250 mV < CSPx − CSREF < 250 mV 8
VMON Linear Range VMONLN 0 2 V 9
Thermal Resistance, Junction-to-Air RJA 68 °C/W JESD 51-5 (1S2P Direct-Attach), 0 LFM 5
Lead Temperature Soldering Reflow (Pb-Free) TSLD 260 °C Reflow (SMD styles only), Pb-Free versions 5
Operating Junction Temperature Range TJ -40 125 °C 5
Operating Ambient Temperature Range TA -10 100 °C 5
Maximum Storage Temperature Range TSTG -55 150 °C 5

CAD (KiCad official)

  • Symbol: NCP81610AMNTXG
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: ncp81610amntxg-etched.step / ncp81610amntxg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp81610amntxg.step / ncp81610amntxg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (32 pp, sha256 3c6042892fdc6ff9, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF