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NCP81258MNTBG

onsemi · Gate Drive ICs · DFN-8-EP(2x2)

NCP81258MNTBG from onsemi, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BST	power_out	Floating bootstrap supply for the high-side gate driver; the external bootstrap capacitor (MLCC greater than 100 nF) connects between BST and SW, and BST is rated -0.3 V to 35 V with respect to GND.
2	PWM	input	Three-state PWM control input: above PWMHI (3.4 V) drives DRVH high, below PWMLO (0.7 V) drives DRVL high, and the mid-state range PWMMID (1.3 V to 2.7 V) enables zero-current detection; the absolute maximum rating is -0.3 V to 6.5 V.
3	EN	bidirectional	Bi-directional enable: EN above ENHI (2.0 V) enables the driver and EN below ENLO (1.0 V) disables DRVH and DRVL, and a UVLO fault pulls this pin low to signal the controller; the absolute maximum rating is -0.3 V to 6.5 V.
4	VCC	power_in	Main supply input with an operating range of 4.5 V to 13.2 V and an absolute maximum of 15 V (16 V for less than 50 ns), requiring a 1 µF bypass capacitor to GND.
5	DRVL	output	Low-side gate drive output for the low-side MOSFET, rated -0.3 V to VCC + 0.3 V (15 V for less than 80 ns).
6	GND	power_in	Bias and reference ground for all signals on the device.
7	SW	passive	Switch node connected to the source of the high-side MOSFET and the drain of the low-side MOSFET, rated -5 V (-10 V for less than 200 ns) to 35 V (40 V for less than 50 ns).
8	DRVH	output	High-side gate drive output for the high-side MOSFET, rated -0.3 V to BST + 0.3 V with respect to SW (-2 V for less than 200 ns).
9	FLAG	passive	Thermal flag (exposed pad) with no electrical connection to the IC; it must be connected to the ground plane.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	DFN-8-EP(2x2)
Category	Power Management ICs
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Main Supply Voltage	VCC	-0.3		15	V	Note 1; 16 V (< 50 ns)	3
Bootstrap Supply Voltage	BST	-0.3		35	V	min wrt/SW; max wrt/GND; 40 V (50 ns) wrt/GND; 15 V wrt/SW	3
Switch Node Voltage	SW	-5		35	V	−10 V (200 ns); 40 V (50 ns)	3
High-Side Driver Output	DRVH	-0.3			V	min wrt/SW; max BST + 0.3 V wrt/SW; −2 V (200 ns) wrt/SW; SW + 15 V (80 ns)	3
Low-Side Driver Output	DRVL	-0.3			V	max VCC + 0.3 V; −5 V (200 ns); 15 V (80 ns)	3
DRVH/DRVL Control Input, Enable Pin	PWM, EN	-0.3		6.5	V		3
Ground	GND	0		0	V		3
Storage Temperature Range	TSTG	-55		150	°C		3
Operating Junction Temperature Range	TJ	-40		150	°C		3
Input Voltage	VCC	4.5		13.2	V		3
Ambient Temperature	TA	-10		125	°C		3
VCC Operation Voltage		4.5		13.2	V		4
Pre-OVP VCC Threshold		2.75		3.2	V		4
VCC Start Threshold	VUVLO	3.8	4.35	4.5	V	VCC rising	4
VCC UVLO Hysteresis	VUVLO_HYS	150	200	250	mV		4
Output Overvoltage Trip Threshold at Startup		2.1	2.25	2.4	V	VCC > Pre−OVP VCC Threshold	4
Bootstrap Diode Forward Voltage		0.1	0.4	0.6	V	VCC = 12 V, Forward bias current = 2 mA	4
PWM Mid-State	PWMMID	1.3		2.7	V		4
PWM Input Low	PWMLO			0.7	V		4
PWM Input High	PWMHI	3.4			V		4
Normal Mode Supply Current	Inormal			12.2	mA	ICC + IBST, EN = 5 V, PWM = 100 kHz, CLOAD = 3 nF for DRVH, 3 nF for DRVL	4
Shutdown Mode Supply Current	Ishutdown		0.5	1.9	mA	ICC + IBST, EN = GND	4
Standby Current 1	Istandby1			2.1	mA	ICC + IBST, EN = 5 V, PWM = 0 V, no loading on DRVH & DRVL	4
Standby Current 2	Istandby2			2.2	mA	ICC + IBST, EN = 5 V, PWM = 5 V, no loading on DRVH & DRVL	4
DRVH Output Impedance, Sourcing Current			2	3.5	Ω	(VBST, VSW) = 12 V	4
DRVH Output Impedance, Sinking Current			1	2	Ω	(VBST, VSW) = 12 V	4
DRVH Rise Time	trDRVH		16	30	ns	VCC = 12 V, 3 nF load, (VBST, VSW) = 12 V	4
DRVH Fall Time	tfDRVH		11	25	ns	VCC = 12 V, 3 nF load, (VBST, VSW) = 12 V	4
DRVH Turn-Off Propagation Delay	tpdlDRVH		8	30	ns	Cload = 3 nF, [PWM = PWMLO] to [VDRVH = 90%]	4
Enable Voltage High	ENHI	2			V		5
Enable Voltage Low	ENLO			1	V		5
Normal Bias Current		-1		1	µA		5
Enable Pin Sink Current			4	30	mA		5
DRVL Output Impedance, Sourcing Current			2	3.5	Ω	VCC = 12 V	5
DRVL Output Impedance, Sinking Current			0.7	1.8	Ω	VCC = 12 V	5
DRVL Rise Time	trDRVL		16	35	ns	VCC = 12 V, CLOAD = 3 nF	5
DRVL Fall Time	tfDRVL		11	20	ns	VCC = 12 V, CLOAD = 3 nF	5
DRVL Turn-Off Propagation Delay	tpdlDRVL		35		ns	CLOAD = 3 nF, [PWM = PWMHI] to [VDRVL = 90%]	5
DRVL Turn-On Propagation Delay	tpdhDRVL		8	30	ns	CLOAD = 3 nF, [VDRVH−VSW] = 1 V to [VDRVL = 10%]	5
DRVH Turn-On Propagation Delay	tpdhDRVH		30		ns	Cload = 3 nF, [VDRVL = 1 V] to [VDRVH−VSW = 10%]	4
HS SW Pull-down Resistance (VCC = 12 V)			37.5		k	SW to PGND	4
HS DRVH Pull-down Resistance (VCC = 12 V)			37.5		k	DRVH to SW, (VBST, VSW) = 0 V	4
HS DRVH Output Impedance, Sourcing Current (VCC = 5 V)			2.5		Ω	(VBST, VSW) = 5 V	4
HS DRVH Output Impedance, Sinking Current (VCC = 5 V)			1.6		Ω	(VBST, VSW) = 5 V	4
DRVH Rise Time (VCC = 5 V)	trDRVL		30		ns	VCC = 5 V, 3 nF load, (VBST, VSW) = 5 V	4
DRVH Fall Time (VCC = 5 V)	tfDRVL		27		ns	VCC = 5 V, 3 nF load, (VBST, VSW) = 5 V	4
DRVH Turn-Off Propagation Delay (VCC = 5 V)	tpdlDRVL		20		ns	CLOAD = 3 nF, [PWM = PWMLO] to [VDRVH = 90%]	4
DRVH Turn-On Propagation Delay (VCC = 5 V)	tpdhDRVL		27		ns	CLOAD = 3 nF, [VDRVL = 1 V] to [VDRVH−VSW = 10%]	4
LS Output Impedance, Sourcing Current (VCC = 5 V)			2.5		Ω	VCC = 5 V	5
LS Output Impedance, Sinking Current (VCC = 5 V)			1		Ω	VCC = 5 V	5
DRVL Rise Time (VCC = 5 V)	trDRVL		30		ns	VCC = 5 V, CLOAD = 3 nF	5
DRVL Fall Time (VCC = 5 V)	tfDRVL		22		ns	VCC = 5 V, CLOAD = 3 nF	5
DRVL Turn-Off Propagation Delay (VCC = 5 V)	tpdlDRVL		27		ns	CLOAD = 3 nF, [PWM = PWMHI] to [VDRVL = 90%]	5
DRVL Turn-On Propagation Delay (VCC = 5 V)	tpdhDRVL		12		ns	CLOAD = 3 nF, [VDRVH−VSW = 1 V] to [VDRVL = 10%]	5
DRVL Pull-down Resistance (VCC = 12 V)			37.5		k	DRVL to GND, VCC = GND	5
EN Hysteresis			500		mV		5
EN High Propagation Delay Time	tpdEN_HI		60		µs	PWM = 0 V, EN going from 0 V to ENHI to DRVL rising to 10%	5
SW Node Leakage Current			20		µA		5
Thermal Resistance, Junction-to-Air	RθJA		74		°C/W	DFN8 2x2 mm; copper area 645 mm2 (1 in2), 1 oz copper, FR4 PCB (Note 2)	3

CAD (KiCad official)

Symbol: NCP81258MNTBG
Footprint: Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm
3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
3D model files: ncp81258mntbg-etched.step / ncp81258mntbg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp81258mntbg.step / ncp81258mntbg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (10 pp, sha256 98abd7123d7e1d31, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF