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docs	ncp81255mntxg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
viewers	ncp81255mntxg: viewers · Ray	2mo ago
ncp81255mntxg-etched.fit.json	ncp81255mntxg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
ncp81255mntxg-etched.glb	ncp81255mntxg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
ncp81255mntxg-etched.step	ncp81255mntxg: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	1mo ago
ncp81255mntxg.glb	Publish 0.1.0 · Ray	2mo ago
ncp81255mntxg.kicad_mod	Publish 0.1.0 · Ray	2mo ago
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package.json	Publish 0.1.0 · Ray	2mo ago
page.json	ncp81255mntxg: specified limits as data (metadata.characteristics, 59 rows from the datasheet) · Ray	26d ago
README.md	ncp81255mntxg: specified limits as data (metadata.characteristics, 59 rows from the datasheet) · Ray	26d ago

NCP81255MNTXG

onsemi · DC-DC Converters · QFN-40(5x5)

NCP81255MNTXG from onsemi, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VR_HOT#	output	Thermal logic (open-drain) output asserted low on over-temperature detected on either TSENSE input. VOL ≤ 0.3 V; leakage ±1 µA when high-Z. Typical VRHOT assert threshold ≈ 472 mV at TSENSE.
2	SDIO	bidirectional	Serial VID data interface (Intel IMVP8 SVID data line). Bidirectional open-drain data pin used by the CPU/PMIC controller.
3	ALERT#	output	Serial VID ALERT# open-drain output. Asserted low by the regulator to alert the CPU controller (SVID master). Typical TSENSE Alert# assert threshold ≈ 491 mV.
4	SCLK	input	Serial VID clock input (Intel IMVP8 SVID clock). Driven by the CPU/PMIC SVID master.
5	PGND	power_in	Power ground. Connected to the source of the internal low-side FET; carries the switching return current.
6	VR_RDY	output	Open-drain regulator-ready output. High indicates the controller is ready to accept Intel proprietary interface commands; requires external pull-up (e.g. 1 kΩ to 3.3 V). VOL ≤ 0.3 V at 4 mA.
7	VIN	power_in	Input voltage to the drain of the integrated high-side FET. Absolute max 30 V. Must be bypassed with ≥22 µF ceramic close to the pin.
8	BST	power_in	Bootstrap capacitor node for the high-side gate driver. Cap required from this pin to SW; BST−SW absolute max 6.5 V.
9	GH	output	High-side FET gate driver output. Swings between SW and BST; internally driven, not for external MOSFET use.
10	SW	power_out	Switch node - return path for the integrated high-side driver, internally connected to the source of the HS FET. Absolute max −0.3 V to 30 V (−2 V < 200 ns).
11	VIN	power_in	Input voltage to HS FET drain. Parallel with pins 7,12,13,14 and flag 42. Bypass with ≥22 µF ceramic close to the pin.
12	VIN	power_in	Input voltage to HS FET drain. Parallel with pins 7,11,13,14 and flag 42.
13	VIN	power_in	Input voltage to HS FET drain. Parallel with pins 7,11,12,14 and flag 42.
14	VIN	power_in	Input voltage to HS FET drain. Parallel with pins 7,11,12,13 and flag 42.
15	PGND	power_in	Power ground - source of internal LS FET. Parallel with pins 5,16,17,18,19,20,26 and flag 43.
16	PGND	power_in	Power ground - source of internal LS FET.
17	PGND	power_in	Power ground - source of internal LS FET.
18	PGND	power_in	Power ground - source of internal LS FET.
19	PGND	power_in	Power ground - source of internal LS FET.
20	PGND	power_in	Power ground - source of internal LS FET.
21	SW	power_out	Switch node output - interconnection between internal HS and LS FETs. Connect to external inductor. Parallel with pins 10,22,23.
22	SW	power_out	Switch node output - interconnection between internal HS and LS FETs. Connect to external inductor.
23	SW	power_out	Switch node output - interconnection between internal HS and LS FETs. Connect to external inductor.
24	GL	output	Low-side FET gate driver output. Internally driven; parallel with pin 25 and flag 44.
25	GL	output	Low-side FET gate driver output. Internally driven; parallel with pin 24 and flag 44.
26	PGND	power_in	Power ground - source of internal LS FET.
27	PVCC	power_in	Gate-driver supply. Bypass with ≥4.7 µF ceramic to GND as close as possible to the pin. Analog supply absolute max 6.5 V.
28	IMAX	input	ICCMAX register programming input. A resistor to ground scales/encodes the ICCMAX value read by the SVID master.
29	TSENSE	input	External temperature sense network input. Sourced with ~120 µA bias; NTC network to GND sets the sensed temperature used for VR_HOT#/ALERT#.
30	DOSC/ADDR/VBOOT	input	Multi-function programming pin: sets switching frequency FSW, the Intel proprietary interface address, and the VBOOT value during start-up. A resistor to GND programs all three values per the datasheet look-up table.
31	PSYS	input	System power signal input. A resistor to ground scales the applied battery-charger/system-power signal. ADC range 0-2 V.
32	VSP	input	Differential output-voltage sense positive input to the internal −gm amplifier. Kelvin to VCC_SENSE. Input range −0.3 V to 3.0 V.
33	VSN	input	Differential output-voltage sense negative input. Kelvin to VSS_SENSE. Input range −0.3 V to 0.3 V.
34	COMP	passive	Loop compensation node - RC network to GND sets the error-amp/control-loop response.
35	ILIM	input	Current-limit programming input. Resistor sets the OCP threshold; ILIMIT threshold internally 1.275-1.325 V.
36	CSN	input	Differential current sense negative input (across output inductor DCR/CS resistor). Also serves as the CSP/CSN ZCD comparator negative input.
37	CSP	input	Differential current sense positive input. Kelvin to the SW side of the sense element. Also serves as the ZCD comparator positive input.
38	IOUT	output	IOUT (current-monitor) analog output / gain programming pin. Resistor to GND sets the IOUT gm gain (nominal 1.0 mS).
39	VCC	power_in	Analog/control-circuit supply input. 4.75 V-5.25 V nominal. Bypass with ≥1 µF ceramic close to the controller. Quiescent 10 mA typ (EN = H).
40	EN	input	Enable input. Upper (enable) threshold ≥0.8 V typ, lower threshold ≤0.3 V, 300 mV hysteresis. Also feeds the VFF (input voltage feed-forward) path.
41	GND	power_in	Exposed thermal/analog ground flag (Flag). Ground of internal control circuits - must be soldered to the analog ground plane.
42	VIN	power_in	Exposed VIN flag (Flag) - internally connected to HS FET drain, parallel with pins 7,11-14. Bypass with ≥22 µF ceramic close to the pin.
43	PGND	power_in	Exposed PGND flag (Flag) - source of internal LS FET, parallel with pins 5,15-20,26.
44	GL	output	Exposed GL flag (Flag) - gate driver output for internal LS FET, parallel with pins 24,25.

Key specifications

Parameter	Value
Manufacturer	onsemi
Package	QFN-40(5x5)
Category	Power Management (PMIC)
Pins	44

Ordering variants

Same part, different packaging or reel option.

NCP81255MNTXG

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power Supply Voltage to PGND	VVIN			30	V		6
Switch Node to PGND	VSW	-0.3		30	V		6
Analog Supply Voltage to GND	VCC, VCCP	-0.3		6.5	V		6
BST to PGND	BST_PGND	-0.3		33	V		6
BST to PGND (transient)	BST_PGND			38	V	< 50 ns	6
BST to SW	BST_SW	-0.3		6.5	V		6
GH to SW	GH	-0.3			V		6
GH to SW (transient)	GH	-2			V	< 200 ns	6
GL to GND	GL	-0.3			V		6
GL to GND (transient)	GL	-2			V	< 200 ns	6
VSN to GND	VSN	-0.3		0.3	V		6
IOUT	IOUT	-0.3		2.5	V		6
PGND to GND	PGND	-0.3		0.3	V		6
Other Pins		-0.3			V		6
Latch Up Current, all pins except digital pins	ILU	-100		100	mA	All pins, except digital pins	6
Latch Up Current, digital pins	ILU	-10		10	mA	Digital pins	6
Operating Junction Temperature Range	TJ	-40		125	°C		6
Operating Ambient Temperature Range	TA	-40		100	°C		6
Storage Temperature Range	TSTG	-40		150	°C		6
ESD Human Body Model	HBM			2000	V		6
ESD Machine Model	MM			200	V		6
ESD Charged Device Model	CDM			1000	V		6
VCC Quiescent Current			10	12	mA	EN = High	7
VCC Quiescent Current			20	40	μA	EN = Low	7
VCC Quiescent Current, PS3				10	mA		7
VCC Quiescent Current, PS4				200	μA		7
VCC UVLO Threshold				4.5	V	VCC Rising	7
VCC UVLO Threshold		4			V	VCC Falling	7
VIN UVLO Threshold				4.25	V	VIN Rising	7
VIN UVLO Threshold		3			V	VIN Falling	7
Enable High Input Leakage Current		-1	0	1	μA	Enable = 0	7
Enable Upper Threshold	VUPPER	0.8			V		7
Enable Lower Threshold	VLOWER			0.3	V		7
Enable Delay Time				2.5	ms	Measure Time from Enable Transitioning HI to VR_RDY High	7
Switching Frequency Range		600		1200	KHz		7
Switching Frequency Accuracy		-10		10	%	600 KHz < FSW < 1.2 MHz	7
ADC Voltage Range		0		2	V		7
ADC Total Unadjusted Error (TUE)		-1		1	%		7
ADC Differential Non-Linearity (DNL)				1	LSB	8-Bit	7
TSENSE Bias Current		116	120	124	μA		7
VR_RDY Output Low Saturation Voltage				0.3	V	IVR_RDY = 4 mA	8
VR_RDY Rise Time				150	ns	External Pull-Up of 1 k to 3.3 V, CTOT = 45 pF, Vo = 10% to 90%	8
VSP Input Voltage Range	VSP	-0.3		3	V		8
VSN Input Voltage Range	VSN	-0.3		0.3	V		8
Differential Voltage Sense Amplifier gm	gm	1.33	1.6	1.86	mS	VSP = 1.2 V	8
IOUT Analog Gain Accuracy		-3		3	%		8
Over Voltage Threshold		360		440	mV	VSP−VSN−VID Setting	8
Under Voltage Threshold		225	290	375	mV	VSP−VSN Falling	8
ILIMIT Threshold		1.275	1.3	1.325	V		8
CSP-CSN ZCD Comparator Offset Accuracy		-1.85		1.85	mV		8
SWN ZCD Comparator Offset Accuracy		-1.5		1.5	mV		9
GH Propagation Delay Time	TGH_d	15	23	30	ns	From GL Falling to GH Rising	9
GL Propagation Delay Time	TGL_d		11	30	ns	From GH Falling to GL Rising	9
High-Side Gate Drive Pull-High On Resistance	RDRV_HH		1.2	2.5	Ω	VBST – VSW = 5 V	9
Low-Side Gate Drive Pull-High On Resistance	RDRV_LH		0.9	2.5	Ω	VCCP – VPGND = 5 V	9
Bootstrap Rectifier Switch Output Low Resistance	Ron_BST	5	13	21	Ω	EN = L or EN = H and DRVL = H	9
Thermal Resistance Junction to Board	RJB		8.2		°C/W	Note 2	6
Thermal Resistance Junction to Ambient	RJA		21.8		°C/W	Note 2	6
Power Dissipation at TA = 25°C	PD		4.59		W	TA = 25°C; Note 3	6

CAD (KiCad official)

Symbol: NCP81255MNTXG
Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
3D model: QFN-40(5x5) (KiCad packages3D, STEP)
3D model files: ncp81255mntxg-etched.step / ncp81255mntxg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncp81255mntxg.step / ncp81255mntxg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: onsemi datasheet (20 pp, sha256 2fc79e9f921d081b, retrieved 2026-08-17, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF